Local bus

All previously described tires have general disadvantage- relatively low throughput. This is due to the fact that the buses were designed with slow processors in mind. Subsequently, the processor speed increased, and the bus characteristics were improved mainly “extensively”, due to the addition of new lines. The obstacle to increasing the bus frequency was great amount released boards that could not work on high speeds exchange (this applies to MCA to a lesser extent, but for the reasons stated above, this architecture did not play a noticeable role in the market). At the same time, in the early 90s, changes occurred in the world of personal computers that required a sharp increase in the speed of exchange with devices:

• creation of a new generation of processors such as Intel 80486, operating at frequencies up to 66 MHz;
• increasing the capacity of hard drives and creating faster controllers;
• development and active promotion of graphical user interfaces to the market ( Windows type or OS/2) led to the creation of new graphics adapters, supporting higher resolution and more colors (VGA and SVGA).

The obvious way out of this situation is the following: to carry out part of the data exchange operations that require high speeds, not through the I/O bus, but through the processor bus, in approximately the same way as connecting external cache. This design is called a local bus. The figures clearly demonstrate the difference between conventional architecture and local bus architecture.

The local bus did not replace previous standards, but complemented them. The main buses in the computer were still ISA or EISA, but one or more local bus slots were added to them. Initially, these slots were used almost exclusively for installing video adapters, and by 1992, several incompatible local bus options had been developed, the exclusive rights to which belonged to the manufacturers. Naturally, such confusion held back the spread of local buses, so VESA (Video Electronic Standard Association) - an association representing more than 100 companies - proposed its local bus specification in August 1992.

VESA local bus (VL-bus)

The main characteristics of VL-bus are as follows.

• Support for 80386 and 80486 series processors. The bus is designed for use in single-processor systems, while the specification provides the ability to support x86-incompatible processors using a bridge chip.
• The maximum number of bus masters is 3 (not including the bus controller). If necessary, it is possible to install several subsystems to support a larger number of masters.
• Although the bus was originally designed to support video controllers, it can also support other devices (for example, hard controllers disk).
• The standard allows bus operation at frequencies up to 66 MHz, however electrical characteristics The VL-bus connector limits it to 50 MHz (this limitation, of course, does not apply to devices integrated into the motherboard).
• The bi-directional 32-bit data bus also supports 16-bit communication. The specification includes the possibility of 64-bit exchange.
• DMA support is provided only for bus masters. The bus does not support special DMA "initiators".
• Maximum theoretical throughput bus - 160 MV/sec (at a bus frequency of 50 MHz), standard - 107 MV/sec at a frequency of 33 MHz.
• Supported batch mode exchange (for 80486 motherboards that support this mode). 5 lines are used to identify the type and speed of the processor, the Burst Last (BLAST#) signal is used to activate this mode. For systems that do not support this mode, the line is set to 0.
• The bus uses a 58-pin MCA connector. A maximum of 3 slots are supported (on some 50 MHz buses, only 1 slot can be installed).
• The VL-bus slot is installed in a line behind the ISA/EISA/MCA slots, so all lines of these buses are available to VL-boards.
• Both the integrated processor cache and the motherboard cache are supported.
• Supply voltage is 5 V. Devices with 3.3 V output are supported provided they can handle 5 V input.

The VL-bus was a huge improvement over the ISA in both performance and design. One of the advantages of the bus was that it made it possible to create cards that work with existing chipsets and do not contain large quantity expensive control logic circuits. As a result, VL cards were cheaper than similar EISA cards. However, this tire was not without its drawbacks, the main ones being the following.

• Orientation towards the 486th processor. VL-bus is hardwired to the 80486 processor bus, which is different from the Pentium and Pentium Pro/Pentium II buses.
• Limited performance. As already mentioned, the real VL-bus frequency is no more than 50 MHz. Moreover, when using processors with a frequency multiplier, the bus uses the main frequency (for example, for the 486DX2-66 the bus frequency will be 33 MHz).
• Circuit restrictions. The quality of signals transmitted over the processor bus is subject to very stringent requirements, which can only be met with certain load parameters for each bus line. According to Intel, installing insufficiently carefully designed VL boards can lead not only to data loss and synchronization problems, but also to system damage.
• Limitation on the number of boards. This limitation also arises from the need to comply with the load restrictions on each line.

Despite the existing shortcomings, VL-bus was the undoubted leader in the market, as it made it possible to eliminate the bottleneck in two subsystems at once - the video subsystem and the hard drive exchange subsystem. However, the leadership was short-lived, as Intel developed its new product - the PCI bus. According to the company, VL-bus was based on 11-year-old technologies and was just a “patch”, a compromise between manufacturers. True, VESA stated that both buses can “coexist” together in one system. Intel agreed that such a neighborhood was possible, but asked a counter-deadly question: “Why?” In fairness, it must be said that PCI was indeed freed from most of the disadvantages inherent in VL-bus.

Organization of input-output

In a computing system consisting of many subsystems, a mechanism is needed for their interaction. These subsystems must exchange data quickly and efficiently. For example, a processor, on the one hand, must be connected to memory; on the other hand, the processor must be connected to I/O devices.

In modern PCs, such a mechanism can be divided into several levels:

System and local buses;

I/O buses.

BIOS (Basic Input/Output System) - the basic input/output system hardwired into ROM (hence the name ROM BIOS). It is a set of programs for checking and maintaining computer hardware, and acts as an intermediary between DOS and the hardware. The BIOS gains control when the motherboard is turned on and reset, tests the board itself and the main components of the computer - video adapter, keyboard, disk controllers and input/output ports, configures the board's Chipset and loads an external operating system. When working under DOS, Windows BIOS controls the main devices; when working under OS/2, UNIX, WinNT, the BIOS is practically not used, performing only initial checking and configuration.

Typically, the motherboard only has a ROM with a Main, System BIOS, which is responsible for the board itself and the FDD, HDD, port and keyboard controllers; V system BIOS System Setup is almost always included - a system configuration program. Video adapters and HDD controllers with ST-506 (MFM) and SCSI interfaces have their own BIOS in separate ROMs; Other boards may also have them - intelligent disk and port controllers, network cards, etc.

One of the simplest mechanisms that allows organizing the interaction of various subsystems is a single central bus, to which all subsystems are connected. Access to such a bus is shared among all subsystems. Such an organization has two main advantages: low cost and versatility. Since such a bus provides a single connection point for different devices, new devices can be easily added, and the same peripheral devices can even be used in different computing systems using the same type of bus. The cost of such an organization is quite low, since a single set of bus lines shared by many devices is used to implement multiple information transfer paths.

The main disadvantage of a single bus organization is that the bus creates a bottleneck, possibly limiting the maximum I/O throughput. If all I/O flow must pass through the central bus, this bandwidth limitation is very real. In commercial systems, where I/O is very frequent, and in supercomputers, where the required I/O speeds are very high due to the high performance of the processor, one of the main design issues is to create a multi-bus system that can satisfy all demands.

One of the reasons for the great difficulty encountered in bus design is that the maximum speed of a bus is primarily limited by physical factors: the length of the bus and the number of connected devices (and therefore the load on the bus). These physical limitations prevent the tires from being accelerated arbitrarily. The requirements for a fast (low latency) I/O system and high throughput are contradictory. Today's large systems use a complex of interconnected buses, each of which provides simplified interaction between various subsystems, high throughput, redundancy (to increase fault tolerance) and efficiency.

Traditionally, buses are divided into buses that provide communication between the processor and memory, and I/O buses. I/O buses can be large, support many types of devices, and usually follow one bus standard. Processor-to-memory buses, on the other hand, are relatively short, typically high-speed, and match the organization of the memory system to provide maximum memory-to-processor channel bandwidth. At the system development stage, for the processor-memory bus all types and parameters of devices that must be interconnected are known in advance, while the I/O bus designer must deal with devices that differ in latency and bandwidth.

As already noted, in order to reduce cost, some computers have a single bus for memory and I/O devices. This tire is often called systemic. Personal computers are usually built on a single system bus in the ISA, EISA or MCA standards. The need to maintain a balance of performance as the speed of microprocessors increases has led to a two-level organization of buses in personal computers based on a local bus. A local bus is a bus that electrically connects directly to the pins of the microprocessor. It usually combines the processor, memory, buffering circuits for the system bus and its controller, as well as some auxiliary circuits. Typical examples of local buses are VL-Bus and PCI.

Let's look at a typical transaction on the bus. A bus transaction includes two parts: sending an address and receiving (or sending) data. Bus transactions are usually determined by the nature of the interaction with memory: a Read transaction transfers data from memory (either to the CPU or an I/O device), a Write transaction writes data to memory. In a Read transaction, the address is first sent to memory along with the appropriate control signals indicating the read. The memory responds by returning data to the bus with appropriate control signals. A Write transaction requires the CPU or I/O device to send an address and data to memory and does not wait for the data to be returned. The CPU usually has to sit idle during the interval between sending the address and receiving the data when performing a read, but often it does not wait for the operation to complete when writing data to memory.

The development of the tire is associated with the implementation of a number of additional features. The decision to select a particular capability depends on cost and performance objectives. The first three options are obvious: separate address and data lines, wider (higher-width) data buses, and bulk transfer mode (sending multiple words) provide increased performance at the expense of increased cost.

A bus master is a device that can initiate read or write transactions. The CPU, for example, is always the bus master. A bus has multiple masters when there are multiple CPUs or when I/O devices can initiate transactions on the bus. If there are multiple such devices, then an arbitration circuit is required to decide who will take over the bus next. Arbitration is often based on either a fixed priority scheme or a more "fair" scheme that randomly selects which master will take over the bus.

Currently, two types of buses are used, differing in the switching method: circuit-switched buses and packet-switched buses, which received their names by analogy with switching methods in data networks. A packet-switched bus with multiple bus masters provides significantly greater throughput than a circuit-switched bus by dividing the transaction into two logical parts: the bus request and the response. This technique is called “split transaction”. (In some systems, this capability is called a connect/disconnect bus or a pipelined bus.) The read transaction is split into a read request transaction, which contains the address, and a memory response transaction, which contains the data. Each transaction must now be marked (tagged) appropriately so that the CPU and memory can tell what is what.

A circuit-switched bus does not split transactions; any transaction on it is an indivisible operation. The master device requests the bus, after arbitration, places an address on it and blocks the bus until the request is serviced. Most of this service time is not spent on bus operations (for example, memory fetch delays). Thus, in buses with circuit switching, this time is simply lost. Split transactions make the bus available to other hosts while memory reads the word at the requested address. This, however, also means that the CPU must fight for the bus to send data, and the memory must fight for the bus to return data. Thus, a split transaction bus has higher throughput, but typically also has higher latency than a bus that is captured for the entire duration of the transaction. A transaction is said to be split because an arbitrary number of other packets or transactions can share the bus between the request and response.

Last question associated with the choice of synchronization type and determines whether the bus is synchronous or asynchronous. If the bus is synchronous, it includes clock signals that are carried on the bus control lines and a fixed protocol that defines the location of the address and data signals relative to the clock signals. Since virtually no additional logic is required to decide what to do next, these buses can be both fast and cheap. However, they have two main disadvantages. Everything on the bus must occur at the same clock frequency, so due to the problem of clock skew, synchronous buses cannot be long. Typically the processor-memory buses are synchronous.

An asynchronous bus, on the other hand, is not clocked. Instead, a start-stop transmission mode and a handshaking protocol are typically used between the source and destination of data on the bus. This design makes it much easier to accommodate a wide variety of devices and extend the bus without worrying about clock signal skew and the clock system. If a synchronous bus can be used, it is usually faster than an asynchronous one due to the lack of bus synchronization overhead for each transaction. The choice of bus type (synchronous or asynchronous) determines not only the throughput, but also directly affects the capacity of the I/O system in terms of physical distance and the number of devices that can be connected to the bus. Asynchronous buses scale better as technology changes. I/O buses are usually asynchronous.

Typically, the number and types of input/output devices in computing systems are not fixed, which allows the user to select required configuration. A computer's I/O bus can be considered an expansion bus that allows for gradual expansion of I/O devices. Therefore, standards play a huge role in allowing computer and I/O device designers to work independently. The emergence of standards is determined by various circumstances.

Sometimes the widespread availability and popularity of a particular machine causes its I/O bus to become a de facto standard. Examples of such buses are the PDP-11 Unibus and the IBM PC-AT Bus. Sometimes standards also arise as a result of certain standardization achievements in some sector of the I/O market. Intelligent Peripheral Interface (IPI) and Ethernet are examples of standards that have emerged as a result of vendor cooperation. The success of a standard is largely determined by its adoption by organizations such as ANSI (National Standards Institute) or IEEE (Institute of Electrical and Electronics Engineers). Sometimes a bus standard may be directly developed by one of the standards committees: an example of such a bus standard is FutureBus.

One of the popular buses of personal computers was the system bus, XT-Bus - the XT architecture bus - the first in the IBM PC family. Relatively simple, supports 8-bit data exchange within a 20-bit (1 MB) address space (denoted as “8/20-bit”), operates at 4.77 MHz. Sharing IRQ lines are generally not possible. Structurally designed in 62-pin connectors.

ISA (Industry Standard Architecture) is the main bus on PC AT computers (another name is AT-Bus). It is an extension of XT-Bus, bit size - 16/24 (16 MB), clock frequency- 8 MHz, maximum throughput -5.55 Mb/s. IRQ separation is also not possible. Non-standard Bus Mastering is possible, but this requires a programmed 16-bit DMA channel. Structurally, it is designed as a 62-pin XT-Bus connector with an adjacent 36-pin expansion connector.

EISA (Enhanced ISA) is a functional and structural extension of ISA. Externally, the connectors have the same appearance as ISA and can accept ISA cards, but in the depth of the connector there are additional rows of EISA contacts, and EISA cards have a higher blade part of the connector with additional rows of contacts. Bit capacity - 32/32 (address space - 4 GB), also operates at a frequency of 8 MHz. Maximum throughput - 32 Mb/s. Supports Bus Mastering - bus control mode from any device on the bus, has an arbitration system for controlling device access to the bus, allows you to automatically configure device parameters, and can separate IRQ and DMA channels.

Bus Mastering- the ability of an external device to independently, without the participation of a processor, control the bus (send data, issue commands and control signals). During the exchange, the device takes over the bus and becomes the main, or master, device. This approach is usually used to free the processor from sending commands and/or data between two devices in the same niche. A special case of Bus Mastering is the DMA mode, which only performs off-processor data transfer; V classical architecture On PC, this is done by the DMA controller, common to all devices. Each Bus Mastering device has its own similar controller, which allows you to get rid of problems with the distribution of DMA channels and overcome the limitations of a standard DMA controller (16-bit, ability to address only the first 16 MB of RAM, low performance, etc.).

MSA (Micro (Channel Architecture - microchannel architecture) - PS/2 bus computers from IBM. Not compatible with any other, bit width - 32/32, (basic - 8/24, the rest - as extensions). Supports Bus Mastering, has arbitration and automatic configuration, synchronous (the duration of the exchange cycle is strictly fixed), maximum throughput - 40 Mb/s. Structurally, it looks like a one- to three-section connector (the same as the VLB). The first, main section is 8-bit ( 90 pins), the second - 16-bit extension (22 pins), the third - 32-bit extension (52 pins). The main section provides lines for transmission sound signals. Additionally, a video expansion connector (20 pins) can be installed next to one of the connectors. EISA and MCA are parallel in many ways; the emergence of EISA was due to IBM's ownership of the MCA architecture.

VLB ( VESA Local Bus - local bus of the VESA standard) - 32-bit (addition to the ISA bus. Structurally, it is an additional connector (116-pin, like the MCA) with the ISA connector. Bit capacity - 32/32, clock frequency - 25..50 MHz, maximum exchange rate - 130 Mb/s. Electrically designed as an extension of the processor local bus - most input and output signals of the processor are transmitted directly to VLB boards without intermediate buffering. This increases the load on the processor output stages and degrades the quality of signals on the local bus and the reliability of exchange through it decreases.Therefore, VLB has a strict limitation on the number of installed devices: at 33 MHz - three, at 40 MHz - two, and at 50 MHz - one, preferably integrated into the motherboard.

PCI (Peripheral Component Interconnect - connection of external components) - development of VLB towards EISA/MCA. Not compatible with any others, bit depth - 32/32 (extended version - 64/64), clock frequency - up to 33 MHz (PCI 2.1 - up to 66 MHz), bandwidth - up to 132 Mb/s (264 Mb/s for 32/32 at 66 MHz and 528 Mb/s for 64/64 at 66 MHz), support for Bus Mastering and auto-configuration. The number of bus connectors on one segment is limited to four. There can be several segments; they are connected to each other via bridges. Segments can be combined into various topologies (tree, star, etc.). The most popular bus at present, it is also used on other computers. The connector is similar to MCA/VLB, but slightly longer (124 pins). The 64-bit connector has an additional 64-pin section with its own key. All connectors and cards for them are divided into those supporting signal levels 5V, 3.3V and universal; the first two types must correspond to each other; universal cards can be placed in any slot.

There is also a MediaBus extension introduced by ASUSTek - an additional connector contains ISA bus signals.

PCMCIA (Personal Computer Memory Card International Association - association of manufacturers of memory cards for personal computers) is an external bus for NoteBook class computers. Another name for a PCMCIA module is PC Card. It is extremely simple, bit depth - 16/26 (address space - 64 MB), supports auto-configuration, it is possible to connect and disconnect devices while the computer is running. The design is a miniature 68-pin connector. The power contacts are made longer, which allows you to insert and remove the card while the computer is powered on.

7.3. I/O buses

Modern computing systems characterized by:

□ rapid growth in the speed of microprocessors and some external devices (for example, for displaying digital full screen video with high quality, a bandwidth of 22 MB/s is required);

□ the emergence of programs that require a large number of interface operations (for example, graphics processing programs in Windows, multimedia).

Under these conditions, the throughput of expansion buses serving several devices simultaneously was not enough for comfortable work for users, since computers began to “think” for a long time. Interface developers have taken the path of creating local buses connected directly to the MP bus, operating at the MP clock frequency (but not at its internal operating frequency) and providing communication with some high-speed devices external to the MP: the main and external memory, video systems, etc.

There are now three basic universal local bus standards: VLB, PCI and AGP.

VLB bus(VL-bus, VESA Local Bus) introduced in 1992 by the Video Electronics Standards Association (VESA - trademark Video Electronics Standards Association) and for this reason it is often called the VESA bus. The VLB bus is essentially an extension of the internal MP bus for communication with a video adapter and, less often, with a hard drive, multimedia cards, and a network adapter. The data bus width is 32 bits, for the address - 30, the actual data transfer speed via VLB is 80 MB/s, theoretically achievable - 132 MB/s (in version 2 - 400 MB/s).

Disadvantages of the VLB bus:

□ targeting only MP 80386, 80486 (not adapted for Pentium class processors);

□ strict dependence on the clock frequency of the MP (each VLB bus is designed only for a specific frequency up to 33 MHz);

□ small number of connected devices - only 4 devices can be connected to the VLB bus;

□ there is no bus arbitration - there are conflicts between connected devices.

PCI bus(Peripheral Component Interconnect, connection of external components) - the most common and universal interface for connecting various devices. Developed in 1993 by Intel. The PCI bus is much more versatile than VLB; allows connection of up to 10 devices; has its own adapter, allowing it to be configured to work with any MP from 80486 to modern Pentium. PCI clock speed is 33 MHz, bit width is 32 bits for data and 32 bits for addresses, expandable to 64 bits, theoretical throughput is 132 MB/s, and in the 64-bit version - 264 MB/s. Modification 2.1 local PCI buses operates at a clock frequency of up to 66 MHz and, with a bit depth of 64, has a throughput of up to 528 MB/s. Plug and Play, Bus Mastering and adapter auto-configuration modes are supported.

Structurally, the bus connector on the system board consists of two consecutive sections of 64 contacts (each with its own key). Using this interface, video cards, sound cards, modems, SCSI controllers and other devices are connected to the motherboard. Typically, the motherboard has several PCI slots. The PCI bus, although local, also performs many of the functions of an expansion bus. Expansion buses ISA, EISA, MCA (and it is compatible with them), in the presence of a PCI bus, are connected not directly to the MP (as is the case when using the VLB bus), but to the PCI bus itself (via an expansion interface). Thanks to this solution, the bus is independent of the processor (unlike VLB) and can work in parallel with the processor bus without accessing it for requests. However, the processor bus load is significantly reduced. For example, the processor works with system memory or cache memory, and at this time over the network HDD information is written. The PCI bus system configuration is shown in Fig. 5.8.

AGP bus(Accelerated Graphics Port - accelerated graphics port) - an interface for connecting a video adapter to a separate AGP trunk that has

Chapter 5. Microprocessors and motherboards

output directly to system memory. A bus based on the PCI v2.1 standard has been developed. The AGP bus can operate at system bus speeds up to 133 MHz and provides the highest graphics transfer rates. Its peak throughput in AGP4x quadruple multiplication mode (4 data blocks are transferred per clock cycle) is 1066 MB/s, and in AGP8x octal multiplication mode it is 2112 MB/s. Compared to the PCI bus, the AGP bus eliminates the multiplexing of address and data lines (in PCI, to reduce the cost of design, the address and data are transmitted over the same lines) and enhances the pipelining of read-write operations, which eliminates the influence of delays in memory modules on the speed of performing these operations.

Rice. 5.8. PCI System Configuration

The AGP bus has two operating modes: DMA And Execute. In DMA mode, the main memory is the video card memory. Graphics objects are stored in system memory, but are copied to local memory cards. The exchange is carried out in large sequential packets. In Execute mode, system memory and local memory of the video card are logically equal. Graphic objects are not copied to local memory, but are selected directly from the system one. In this case, you have to select relatively small randomly located pieces from memory. Since system memory is allocated dynamically, in 4 KB blocks, this mode To ensure acceptable performance, a mechanism is provided that maps sequential addresses of fragments to real addresses of 4-kilobyte blocks in system memory. This procedure is performed using a special table (Graphic Address Re-mapping Table or GART) located in memory. The interface is designed as a separate connector into which an AGP video adapter is installed.
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The system configuration with the AGP bus is shown in Fig. 5.9.

In-machine system and peripheral interfaces

Rice. 5.9. System configuration with AGP bus

Everything said above regarding tires is summarized in table. 5.4. Table 5.4. Main characteristics of tires

Local buses - concept and types. Classification and features of the category "Local buses" 2017, 2018.

ISA, MCA and EISA buses have one common drawback - relatively low performance. The four types of buses described in the following sections are local. The main types of local buses used in PCs include the following.

• VL-Bus (VESA Local Bus)

This limitation existed back in the days of the first PCs, in which the I/O bus operated at the same speed as the processor bus. The speed of the processor bus increased, and the characteristics of I/O buses improved mainly due to an increase in their bit capacity. It was necessary to limit the speed of the buses because most of the adapter boards produced could not operate at increased data exchange rates.

Some users are haunted by the thought that their computer is running slower than it can. However, the speed of the I/O bus does not matter in most cases. For example, when working with a keyboard or mouse, high performance is not required, since in this situation the computer's performance is determined by the user. It is really only necessary in subsystems where it is important high speed data exchange, for example in graphics and disk controllers.

The problem associated with bus speed has become relevant due to the proliferation of graphical user interfaces (for example, Windows). They process such large amounts of data that the I/O bus becomes the system's bottleneck. Ultimately, the high performance of a processor with a clock frequency of 66 or even 450 MHz turns out to be completely useless, since data is transferred on the I/O bus several times slower (the clock frequency is about 8 MHz).

An obvious solution to this problem is to have some of the data exchange carried out not through the I/O bus connectors, but through additional high-speed connectors. The best approach to solving this problem is to locate the additional I/O connectors on the fastest bus, i.e. on the processor bus (this is similar to connecting an external cache memory). The corresponding block diagram is shown in the figure below. This design is called a local bus because external devices(adapter boards) now have access to the processor bus (i.e. the bus closest to it). Of course, the local bus connectors must be different from the I/O bus slots so that “slow” adapter cards cannot be inserted into them.

It is interesting to note that the first 8- and 16-bit ISA buses had a local bus architecture. These systems used the processor bus as the primary bus, and all devices operated at processor speed. When the clock speed in ISA systems exceeded 8 MHz, the main computer bus was separated from the processor bus, which could no longer perform these functions. Introduced in 1992, an enhanced version of the ISA bus, called VESA Local Bus (or VL-Bus), marked a return to local bus architecture. Subsequently, the local VESA bus was replaced by the PCI bus, and its addition was the AGP bus.

Note!

To organize a local bus in a computer, it is not at all necessary to install expansion slots: a device that uses a local bus can be mounted directly on the motherboard. The first local bus computers used exactly this approach.

The local bus does not replace previous standards, but complements them. The main computer buses, as before, remain ISA and EISA, but one or more local bus slots are added to them. At the same time, compatibility with older expansion cards is maintained, and high-speed adapters are installed in local bus slots, while all their capabilities are realized. Thus, until now the most common connectors are AGP, PCI and ISA. Older boards sometimes turn out to be compatible with new connectors, but all the capabilities of the local AGP and PCI buses allow you to use only new adapter models. As the popularity of the ISA bus decreases and emphasis shifts to the LPC interface, the role of the ISA bus is gradually reduced, and other buses are used instead.

Performance GUI user experience of Windows or Linux (such as KDE or GNOME) has increased significantly after ISA video adapters were replaced by PCI and AGP adapters.

SPECIFICATIONS

LOCAL BUS

PERSONAL COMPUTER

The bottleneck of modern

personal computers -

input/output bus. Two con-

supervising specifications

designed to increase

throughput

input/output buses.

Mid-June 1992 Intel Corporation and VESA (Video Electronic Standards Association, San Jose, California) have proposed draft local bus specifications, solving the problem increasing the productivity of personal computers by improving the data input/output subsystem.

Intel presented its PCI (Peripheral Component Interconnect) interface specification, and the VESA association presented its VL-Bus local bus specification. Both Intel and VESA hope that what they offer technical solutions will become an industry standard.

The specifications are not compatible with each other and will most likely compete for the sympathy of developers. Some observers have noted that the industry may be in for a repeat of the "tire war" that broke out a few years ago between EISA and MCA tires.

The local bus is designed to provide direct processor access to peripheral devices (for example, graphics or network adapters), bypassing the arbitration provided in ISA, EISA or MCA buses. In theory, a 32-bit local bus can transmit and receive data from peripheral devices at the maximum speed of a 386 or 486 CPU.

The PCI bus was developed by Intel to provide OEMs and motherboard manufacturers with a standard way to connect additional circuitry to the PC motherboard to maximize system performance. For example, using the local bus located on the system board, the manufacturer can connect to the computer network interface or graphics adapter.

The VL-Bus of the VESA Association is designed to play the role of a standard hardware interface that allows you to install adapters from independent companies directly into the motherboard sockets, as well as place additional components on the motherboard.

BOTTLE POINT ELIMINATION

As microprocessor speeds increase, the I/O bus becomes a bottleneck, negatively impacting overall system performance. Performance on modern desktop PCs is typically hampered by slow processing speeds graphic images and access to disk drives. The LAN throughput is determined by the network schedule, communication protocol and access time to the drives.

Currently, PC I/O functions are implemented using standard ISA, EISA or MCA expansion buses. The efficient throughput of these machines can only be increased with the help of additional intelligence and built-in specialized processors.

Today no one is going to give up standard expansion buses, but it is quite obvious that you can get a significant performance gain by connecting graphics adapters, network controllers, disk drives and SCSI interface controllers to the local bus, which is a channel for direct data exchange with the CPU.

Some OEMs and printed circuit boards have already announced products containing original local buses, but the development of this direction is still hampered by the lack of a standard interface. This state of affairs means high costs for the consumer. similar systems And limited opportunities choice.

VL-BUS

VESA ASSOCIATIONS

The VL-Bus specification is essentially a hardware interface standard. According to Ron McCabe, chairman of the VESA VL-Bus subcommittee, this specification regulates the requirements for the architecture and physical components of the interface with the CPU.

Via local bus CPU

computer receives direct

access to peripheral devices.

40 companies took part in the development of the draft VL-Bus specification. According to VESA officials, the final version was expected to be ready in 1994. Initially, this bus was used to build network servers, image processing and multimedia systems.

The VL-Bus has a high throughput of over 130 MB/s. VESA experts say that depending on the type of peripheral device, the expected performance increase will range from 50 to 600%. The VL-Bus is designed to operate at frequencies up to 66 MHz. At a frequency of 33 MHz, it allows you to perform write operations without wait cycles and with one wait cycle, read operations, and at a frequency of 66 MHz - write and read operations with one wait cycle. There is a bus capture mode in which the device takes control of system resources without the participation of the CPU.

Installing a disk controller with SCSI interface and VL-Bus in network server can increase network speed characteristics by 15% due to increased communication speed with drives. This occurs by reducing the likelihood of collisions and retries of data transmission. The actual speed of information transfer on the line will not change, but the reduction in the probability of waiting means that the network is capable of more intense load and responds to events more effectively. One of the key elements that distinguishes the VL-Bus specification from Intel's PCI specification is the presence of a standard connector. The design of the connectors is similar to that of the MCI bus connectors. Up to three boards can be connected to the bus via connectors.

The disadvantage of the VL-Bus is the complexity of the circuit implementation and the need to develop new sets of integrated circuits. Motherboard and OEM manufacturers must design new products to meet the new specification. This, however, does not require redesigning the software.

VESA has been successful in attracting a significant number of OEMs and peripheral manufacturers. Integrated circuit kits appeared in late 1992, and end-user products in 1993.

Now the specification is expanding - a 64-bit data exchange mode is being introduced and there are IC converters (for communication between the CPU and a peripheral device), making the VL-Bus compatible with Intel's PCI bus.

LOCAL PCI BUS

INTEL COMPANIES

By coincidence, Intel announced its PCI bus specification also in June 1992. at the PC Expo.

The Intel Local Bus is a typical internal bus that allows OEMs to install components directly on the motherboard, bypassing the CPU-memory bus. The specification requires that the interface between the CPU and the connected peripheral device be carried out using a so-called bridge integrated circuit.

This solution, according to Michael Bailey, Intel's PCI product marketing manager, provides the I/O bandwidth needed without hogging the CPU. The processor can then work with main memory at full speed.

Intel specialists say that PCI is a multiplexed 32-bit bus that can be expanded to 64 bits. The bus is capable of operating in synchronous mode at frequencies up to 33 MHz. For the 32-bit bus version, the throughput is 132 MB/s.

When exchanging data, the CPU gains direct access to devices connected to the PCI bus, which can be located in the memory address space or in the I/O device space. In bus capture mode, PCI bus masters gain direct access to main memory. Pavement integrated circuit can also provide optional buffering and centralized bus arbitration functions.

The PCI specification does not explicitly define a connector type for printed circuit boards, but Intel states that it had a specific connector type in mind when developing this specification. In the future, the specification plans to include requirements for power management for battery-powered machines and voltage management for low-voltage ICs.

WHO IS FIRST?

According to industry observers, from a technical point of view, the VL-Bus and PCI buses differ slightly. They provide comparable data transfer rates, the same bit depth transmitted information, direct memory access with delays of 1 or 0.5 clock cycles.

The real success of the bus will be determined by how well the data exchange drivers are built and the mode is used direct access to memory.

"The VL-Bus is taking the lead," says John Peddie, publisher and editor of The PC Graphics Report. The reason is simple: This tire is not some fantasy, it already exists. The main selling point of the VESA specification is that the connector for the bus has already been selected.

LITERATURE:

1. Computer Sources, August 1994 (Magazine)

2. PS Magazine, N1 1995

3. PC World, N3.5 1994