Types of dynamic RAM. Dynamic random access memory device

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DYNAMIC RAM

PC high-speed RAM chip, which is different

in that it loses its contents if it is not read within 2 milliseconds.

The microcircuits are organized in the form of a square matrix, the intersection of each column and row of which specifies the address of the corresponding elementary cells. Reading the row address occurs when a row pulse is applied to the matrix input, and reading the column address occurs when a column pulse is applied. Row and column addresses are transmitted over a special multiplexed address bus MA (Multiplexed Address). Dynamic memory is performed in synchronous and asynchronous variants. In the latter case, setting the address, supplying control signals and reading/writing data

can be executed at arbitrary times.

TYPES OF DYNAMIC RAM

FPU DRAH "Dynamic RAM with fast page access": the main type of video memory, identical to that used in motherboards. Uses asynchronous (random) access to data storage cells, in which control signals are not strictly tied to the system clock frequency.

EDO DRAH/RAH "Extended Availability RAM": A dynamic memory chip that is different from conventional DRAM. Technical support for automated systems with an increased ability to work in the so-called page mode (associated with a reduction in the number of cycles when sampling adjacent words of text). As a result, the machine's productivity increases (by about 5%). Used as the main memory of PCs based on Pentium and Pentium Pro microprocessors, as well as in video cards with a bus frequency of 40-50 MHz. The maximum throughput is about 105 MB/s.

DDR SDRAM "Double Data Rate Synchronous Dynamic RAM" or "Advanced Synchronous Dynamic RAM" differs from SDRAH in that the latter has a small static memory added to act as a cache memory. Using an additional cache allows you to reduce latency and achieve a peak operating frequency of 200 MHz. The purpose of this caching is to store frequently accessed data and minimize access to slower DRAM. The throughput and speed of operation of this combination is also doubled due to the fact that when exchanging data between the SRAM cache and the DRAM itself there can be

a bus of greater width is used than between the SRAM cache and the controller

DRAM. This type of developing memory has gained the greatest popularity in the production of graphics accelerators.

FB-DIMM "Fully Buffered Memory" improves RAM performance by using dual-channel access technology. The need for this type of memory arose due to a reduction in the number of modules that can be placed on one microprocessor northbridge controller.

VRAH "Video RAM" or "Video Memory": high-speed computer random access memory, which is the result of the development of dynamic RAM for the computer's graphics subsystem and its multimedia applications. It is sometimes also called "dual-port DRAM". It differs from conventional dynamic RAM (DRAH) schemes in the ability to simultaneously perform write and read operations due to the presence of two inputs (ports), which provides a significant (approximately twofold) increase in system performance. Used in graphics adapters. Its parameters: bus frequency 25-33 MHz, maximum throughput 120 MB/s. VRAM is one of the most expensive types of memory.

Unlike SRAM, the address of a DRAM cell is transferred to the chip in two steps - first the column address, and then the row, which makes it possible to reduce the number of address bus pins by approximately half, reduce the size of the package and place it on motherboard more chips. This, of course, leads to a decrease in performance, since it takes twice as long to transfer the address. To indicate which part of the address is transmitted at a certain moment, two auxiliary signals RAS and CAS are used. When accessing a memory cell, the address bus is set to the address of the row. After the processes on the bus have stabilized, the RAS signal is applied and the address is written to the internal register of the memory chip. The address bus is then set to the column address and the CAS signal is issued. Depending on the state of the WE line, data is read from the cell or written to the cell (the data must be placed on the data bus before writing). The interval between setting the address and issuing the RAS (or CAS) signal is determined by the technical characteristics of the microcircuit, but usually the address is set in one cycle of the system bus, and the control signal in the next. Thus, to read or write one cell of dynamic RAM, five clock cycles are required, in which the following occurs: issuing a row address, issuing a RAS signal, issuing a column address, issuing a CAS signal, performing a read/write operation (in static memory, the procedure takes only two up to three measures).

Rice. 5.10. Classification of dynamic RAM: a - chips for main memory; b- chips for video adapters

You should also remember the need to regenerate data. But along with the natural discharge of the capacitor, the electronic device also leads to a loss of charge over time when reading data from DRAM, so after each read operation the data must be restored. This is achieved by writing the same data again immediately after reading it. When reading information from one cell, the data of the entire selected row is actually output at once, but only those that are in the column of interest are used, and all the rest are ignored. Thus, a read operation from a single cell destroys the entire row's data and must be recovered. Data regeneration after reading is performed automatically by the interface logic of the chip, and this happens immediately after reading the line. Now let's look at the different types of dynamic memory chips, starting with system DRAM, that is, chips designed to be used as main memory. At the initial stage, these were asynchronous memory chips, the operation of which is not strictly tied to the clock pulses of the system bus.

Asynchronous dynamic RAM. Asynchronous dynamic RAM chips are controlled by RAS and CAS signals, and their operation, in principle, is not directly related to bus clock pulses. Asynchronous memory is characterized by additional time spent on interaction between memory chips and the controller. Thus, in an asynchronous circuit, the RAS signal will be generated only after a clock pulse arrives at the controller and will be perceived by the memory chip after some time. After this, the memory will produce data, but the controller will be able to read it only upon the arrival of the next clock pulse, since it must work synchronously with the rest of the VM devices. Thus, there are slight delays during the read/write cycle due to the memory controller and memory controller waiting.

DRAM chips. The first dynamic memory chips used the simplest method of data exchange, often called conventional. It allowed reading and writing a memory line only every fifth clock cycle (Fig. 5.11, A). The steps of such a procedure have been described previously. Traditional DRAM corresponds to the formula 5-5-5-5. Microcircuits of this type could operate at frequencies up to 40 MHz and, due to their slowness (access time was about 120 seconds), did not last long.

FPMDRAM chips. Dynamic RAM chips that implement FPM mode are also early types of DRAM. The essence of the regime was shown earlier. Reading circuit for FPM DRAM (Fig. 5.11, 6) described by the formula 5-3-3-3 (14 bars in total). The use of a fast page access scheme reduced access time to 60 seconds, which, taking into account the ability to operate at higher bus frequencies, led to an increase in memory performance compared to traditional DRAM by approximately 70%. This type of chip was used in personal computers until about 1994.

EDO DRAM chips. The next stage in the development of dynamic RAM was ICs with hyperpage access mode(HRM, Hyper Page Mode), better known as EDO (Extended Data Output - extended data retention time at the output). The main feature of the technology is the increased time of data availability at the output of the microcircuit compared to FPM DRAM. In FPM DRAM chips, the output data remains valid only when the CAS signal is active, which is why the second and subsequent row accesses require three clock cycles: a CAS switch to the active state, a data read clock, and a CAS switch to the inactive state. In EDO DRAM, on the active (falling) edge of the CAS signal, the data is stored in an internal register, where it is stored for some time after the next active edge of the signal arrives. This allows you to use stored data when CAS is already in an inactive state (Fig. 5.11, b). In other words, timing parameters are improved by eliminating cycles of waiting for the moment of data stabilization at the output of the microcircuit.

The reading pattern of EDO DRAM is already 5-2-2-2, which is 20% faster than FPM. Access time is about 30-40 seconds. It should be noted that the maximum system bus frequency for EDO DRAM chips should not exceed 66 MHz.

BEDO DRAM chips. EDO technology has been improved by VIA Technologies. The new modification of EDO is known as BEDO (Burst EDO). The novelty of the method is that during the first access, the entire line of the microcircuit is read, which includes consecutive words of the package. The sequential transfer of words (switching columns) is automatically monitored by the internal counter of the chip. This eliminates the need to issue addresses for all cells in a packet, but requires support from external logic. The method allows you to reduce the time of reading the second and subsequent words by another clock cycle (Fig. 5.11, G), due to which the formula takes the form 5-1-1-1.

EDRAM chips. A faster version of DRAM was developed by Ramtron's subsidiary, Enhanced Memory Systems. The technology is implemented in FPM, EDO and BEDO variants. The chip has a faster core and internal cache memory. The presence of the latter is the main feature of the technology. The cache memory is static memory (SRAM) with a capacity of 2048 bits. The EDRAM core has 2048 columns, each of which is connected to an internal cache. When accessing any cell, the entire row (2048 bits) is read simultaneously. The read line is entered into SRAM, and the transfer of information to cache memory has virtually no effect on performance, since it occurs in one clock cycle. When further accesses to cells belonging to the same row are made, the data is taken from the faster cache memory. The next access to the kernel occurs when accessing a cell that is not located in a line stored in the chip's cache memory.

The technology is most effective when reading sequentially, that is, when the average access time for a chip approaches the values characteristic of static memory (about 10 ns). The main difficulty is incompatibility with controllers used when working with other types of DRAM.

Synchronous dynamic RAM. In synchronous DRAM, information exchange is synchronized by external clock signals and occurs at strictly defined points in time, which allows you to take everything from the bandwidth of the processor-memory bus and avoid wait cycles. Address and control information is recorded in the memory IC. After which the response of the microcircuit will occur through a clearly certain number clock pulses, and the processor can use this time for other actions not related to memory access. In the case of synchronous dynamic memory, instead of the duration of the access cycle, they talk about the minimum permissible period of the clock frequency, and we are already talking about a time of the order of 8-10 ns.

SDRAM chips. The abbreviation SDRAM (Synchronous DRAM) is used to refer to “regular” synchronous dynamic RAM chips. The fundamental differences between SDRAM and the asynchronous dynamic RAM discussed above can be reduced to four points:

 synchronous method of data transfer to the bus;

 conveyor mechanism for packet forwarding;

 use of several (two or four) internal memory banks;

 transferring part of the functions of the memory controller to the logic of the microcircuit itself.

Memory synchronicity allows the memory controller to “know” when data is ready, thereby reducing the costs of waiting and searching cycles for data. Since data appears at the output of the IC simultaneously with clock pulses, the interaction of memory with other VM devices is simplified.

Unlike BEDO, the pipeline allows packet data to be transferred clock by clock, allowing the RAM to operate smoothly at higher frequencies than asynchronous RAM. The advantages of a pipeline are especially important when transmitting long packets, but not exceeding the length of the chip line.

A significant effect is achieved by dividing the entire set of cells into independent internal arrays (banks). This allows you to combine access to a cell in one bank with preparation for the next operation in the remaining banks (recharging control circuits and restoring information). The ability to keep multiple lines of memory open simultaneously (from different banks) also helps improve memory performance. When accessing banks alternately, the frequency of accessing each of them individually decreases in proportion to the number of banks and SDRAM can operate at higher frequencies. Thanks to the built-in address counter, SDRAM, like BEDO DRAM, allows you to read and write to batch mode, and in SDRAM the packet length varies and in batch mode it is possible to read an entire memory line. The IC can be characterized by the formula 5-1-1-1. Although the formula for this type of dynamic memory is the same as BEDO, the ability to operate at higher frequencies means that SDRAM with two banks at a bus clock speed of 100 MHz can almost double the performance of BEDO memory.

DDR SDRAM chips. An important step in the further development of SDRAM technology was DDR SDRAM (Double Data Rate SDRAM - SDRAM with double the data transfer rate). Unlike SDRAM, the new modification produces data in burst mode on both edges of the synchronization pulse, due to which the throughput doubles. There are several DDR SDRAM specifications, depending on the system bus clock speed: DDR266, DDR333, DDR400, DDR533. Thus, the peak bandwidth of a DDR333 memory chip is 2.7 GB/s, and for DDR400 it is 3.2 GB/s. DDR SDRAM is currently the most common type of dynamic memory in personal VMs.

RDRAM, DRDRAM microcircuits. The most obvious ways to increase the efficiency of a processor with memory are to increase the bus clock frequency or the sampling width (the number of simultaneously transferred bits). Unfortunately, attempts to combine both options encounter significant technical difficulties (as the frequency increases, the problems of electromagnetic compatibility become worse; it becomes more difficult to ensure that all parallelly sent bits of information arrive at the same time to the consumer). Most synchronous DRAMs (SDRAM, DDR) use wide sampling (64 bits) at a limited bus frequency.

A fundamentally different approach to building DRAM was proposed by Rambus in 1997. It focuses on increasing the clock speed to 400 MHz while reducing the sample width to 16 bits. The new memory is known as RDRAM (Rambus Direct RAM). There are several varieties of this technology: Base, Concurrent and Direct. In all, clocking is carried out on both edges of clock signals (as in DDR), due to which the resulting frequency is 500-600, 600-700 and 800 MHz, respectively. The first two options are almost identical, but the changes in Direct Rambus (DRDRAM) technology are quite significant.

First, let's look at the fundamental points of RDRAM technology, focusing mainly on the more modern version - DRDRAM. The main difference from other types of DRAM is the original data exchange system between the core and the memory controller, which is based on the so-called “Rambus channel” using an asynchronous block-oriented protocol. At the logical level, information between the controller and memory is transferred in packets.

There are three types of packages: data packages, row packages and column packages. Packets of rows and columns are used to transmit commands from the memory controller to control the rows and columns of the array of storage elements, respectively. These commands replace the conventional chip control system using RAS, CAS, WE and CS signals.

SLDRAM chips. A potential competitor to RDRAM as a memory architecture standard for future personal VMs is a new type of dynamic RAM developed by the SyncLink Consortium, a consortium of VM manufacturers, known by the abbreviation SLDRAM. Unlike RDRAM, the technology of which is the property of Rambus and Intel, this standard is open. On system level the technologies are very similar. Data and commands from the controller to memory and back to SLDRAM are transmitted in packets of 4 or 8 messages. Commands, address and control signals are sent over a unidirectional 10-bit command bus. Read and write data is transmitted over a bidirectional 18-bit data bus. Both buses operate at the same frequency. For now, this frequency is still 200 MHz, which, thanks to DDR technology, is equivalent to 400 MHz. The next generations of SLDRAM should operate at frequencies of 400 MHz and higher, that is, provide an effective frequency of more than 800 MHz.

Up to 8 memory chips can be connected to one controller. To avoid delays in signals from chips further away from the controller, the timing characteristics for each chip are determined and entered into its control register when the power is turned on.

ESDRAM chips. This is a synchronous version of EDRAM that uses the same techniques to reduce access time. A write operation, unlike a read operation, bypasses the cache, which increases ESDRAM performance when resuming reading from a line already in the cache. Thanks to the presence of two banks in the chip, downtime due to preparation for read/write operations is minimized. The disadvantages of the microcircuit under consideration are the same as those of EDRAM - the complication of the controller, since it must take into account the possibility of preparing to read a new kernel line into the cache memory. In addition, with an arbitrary sequence of addresses, the cache memory is used inefficiently.

CDRAM chips. This type of RAM was developed by Mitsubishi Corporation, and it can be considered as a revised version of ESDRAM, free from some of its imperfections. The capacity of the cache memory and the principle of placing data in it have been changed. The capacity of a single cache block has been reduced to 128 bits, so the 16-kilobit cache can simultaneously store copies of 128 memory locations, allowing for more efficient use of cache memory. Replacement of the first memory section placed in the cache begins only after the last (128th) block is filled. The means of access have also changed. Thus, the chip uses separate address buses for the static cache and the dynamic core. Transferring data from the dynamic core to cache memory is combined with issuing data to the bus, so frequent but short transfers do not reduce the performance of the IC when reading large amounts of information from memory and put CDRAM on par with ESDRAM, and when reading at selective addresses, CDRAM clearly wins. It should be noted, however, that the above changes led to even greater complexity of the memory controller.

There is much more dynamic memory in a computer than static memory, since DRAM is used as the main memory of the VM. Like SRAM, dynamic memory consists of a core (an array of electronic devices) and interface logic (buffer registers, data reading amplifiers, regeneration circuits, etc.). Although the number of types of DRAM has already exceeded two dozen, their cores are organized almost identically. The main differences are related to the interface logic, and these differences are also due to the scope of application of the microcircuits - in addition to the main memory of the VM, dynamic memory ICs are included, for example, in video adapters. The classification of dynamic memory chips is shown in Fig. 72.

To evaluate the differences between types of DRAM, let’s first look at the algorithm for working with dynamic memory. For this we will use Fig. 68.

Unlike SRAM, the address of a DRAM cell is transferred to the chip in two steps - first the column address, and then the row, which makes it possible to reduce the number of address bus pins by approximately half, reduce the size of the case and place a larger number of chips on the motherboard. This, of course, leads to a decrease in performance, since it takes twice as long to transfer the address. To indicate which part of the address is transmitted at a certain moment, two auxiliary signals RAS and CAS are used. When accessing a memory cell, the address bus is set to the address of the row. After the processes on the bus have stabilized, the RAS signal is applied and the address is written to the internal register of the memory chip. The address bus is then set to the column address and the CAS signal is issued. Depending on the state of the WE line, data is read from the cell or written to the cell (the data must be placed on the data bus before writing). The interval between setting the address and issuing the RAS (or CAS) signal is determined by the technical characteristics of the microcircuit, but usually the address is set in one cycle of the system bus, and the control signal in the next. Thus, to read or write one cell of dynamic RAM, five clock cycles are required, in which the following occurs: issuing a row address, issuing a RAS signal, issuing a column address, issuing a CAS signal, performing a read/write operation (in static memory, the procedure takes only two up to three measures).

Rice. 72. Classification of dynamic RAM: a) – chips for main memory; b) – microcircuits for video adapters.

Now let's look at the different types of dynamic memory chips, starting with system DRAM, that is, chips designed to be used as main memory. At the initial stage, these were asynchronous memory chips, the operation of which is not strictly tied to the clock pulses of the system bus.

DRAM chips. The first dynamic memory chips used the simplest method of data exchange, often called conventional. It allowed reading and writing a memory line only every fifth clock cycle . The steps of such a procedure have been described previously. Traditional DRAM corresponds to the formula 5-5-5-5. Microcircuits of this type could operate at frequencies up to 40 MHz and, due to their slowness (access time was about 120 ns), did not last long.

FPMDRAM chips. Dynamic RAM chips that implement FPM mode are also early types of DRAM. The essence of the regime was shown earlier. The read pattern for FPM DRAM is described by the formula 5-3-3-3 (14 clock cycles in total). The use of a fast page access scheme reduced access time to 60 ns, which, taking into account the ability to operate at higher bus frequencies, led to an increase in memory performance compared to traditional DRAM by approximately 70%. This type of chip was used in personal computers until about 1994.

EDO DRAM chips. The next stage in the development of dynamic RAM was ICs with hyperpage access mode(HRM, Hyper Page Mode), better known as EDO (Extended Data Output - extended data retention time at the output). The main feature of the technology is the increased time of data availability at the output of the microcircuit compared to FPM DRAM. In FPM DRAM chips, the output data remains valid only when the CAS signal is active, which is why the second and subsequent row accesses require three clock cycles: a CAS switch to the active state, a data read clock, and a CAS switch to the inactive state. In EDO DRAM, on the active (falling) edge of the CAS signal, the data is stored in an internal register, where it is stored for some time after the next active edge of the signal arrives. This allows the stored data to be used when the CAS is already in an inactive state. In other words, timing parameters are improved by eliminating cycles of waiting for the moment of data stabilization at the output of the microcircuit.

The reading pattern of EDO DRAM is already 5-2-2-2, which is 20% faster than FPM. Access time is about 30-40 ns. It should be noted that the maximum system bus frequency for EDO DRAM chips should not exceed 66 MHz.

Synchronous dynamic RAM. In synchronous DRAM, information exchange is synchronized by external clock signals and occurs at strictly defined points in time, which allows you to take everything from the bandwidth of the processor-memory bus and avoid wait cycles. Address and control information is recorded in the memory IC. After which the response of the microcircuit will occur through a clearly defined number of clock pulses, and the processor can use this time for other actions not related to accessing memory. In the case of synchronous dynamic memory, instead of the duration of the access cycle, they talk about the minimum permissible period of the clock frequency, and we are already talking about a time of the order of 8-10 ns.

· synchronous method of data transfer to the bus;

· conveyor mechanism for packet forwarding;

· use of several (two or four) internal memory banks;

· transfer of part of the functions of the memory controller to the logic of the microcircuit itself.

A significant effect is achieved by dividing the entire set of cells into independent internal arrays (banks). This allows you to combine access to a cell in one bank with preparation for the next operation in the remaining banks (recharging control circuits and restoring information). The ability to keep multiple lines of memory open simultaneously (from different banks) also helps improve memory performance. When accessing banks alternately, the frequency of accessing each of them individually decreases in proportion to the number of banks and SDRAM can operate at higher frequencies. Thanks to the built-in address counter, SDRAM, like BEDO DRAM, allows reading and writing in burst mode, and in SDRAM the burst length varies and in burst mode it is possible to read an entire memory line. The IC can be characterized by the formula 5-1-1-1. Although the formula for this type of dynamic memory is the same as BEDO, the ability to operate at higher frequencies means that SDRAM with two banks at a bus clock speed of 100 MHz can almost double the performance of BEDO memory.

The GE array is divided into banks. Their number in a crystal with a capacity of 64 Mbit is 8 independent or 16 dual banks. In dual bank^, the pair of banks share common read/write amplifiers. The internal core of the chip has a 128-bit data bus, which allows 16 bytes to be transferred at each column address. When recording, you can use a mask in which each bit corresponds to one byte of the packet. Using the mask, you can specify how many bytes of the packet and which bytes should be written to memory.

The data, row and column lines in the channel are completely independent, so row commands, column commands and data can be transmitted simultaneously, and for different banks of the chip. Column packets contain two fields and are transmitted over five lines. The first field specifies the main write or read operation. The second field contains either an indication of the use of a record mask (the mask itself is transmitted over the data lines), or an extended operation code that defines an option for the main operation. String packets are divided into activation, cancellation, regeneration and power mode switching commands. Three lines are allocated for transmitting string packets.

The write operation can immediately follow the read - only a delay is needed for the time the signal travels through the channel (from 2.5 to 30 ns depending on the length of the channel). To equalize delays in the transmission of individual bits of the transmitted code, the conductors on the board must be positioned strictly in parallel, have the same length (the length of the lines should not exceed 12 cm) and meet strict requirements defined by the developer.

Each write in the channel can be pipelined, with the first data packet having a latency of 50 ns, and the remaining read/write operations occurring continuously (latency is only introduced when changing from a write to a read operation, and vice versa).

Available publications mention Intel work and Rambus on a new version of RDRAM called nDRAM that will support data transfer rates up to 1600 MHz.

SLDRAM chips. A potential competitor to RDRAM as a memory architecture standard for future personal VMs is a new type of dynamic RAM developed by the SyncLink Consortium, a consortium of VM manufacturers, known by the abbreviation SLDRAM. Unlike RDRAM, the technology of which is the property of Rambus and Intel, this standard is open. At the system level, the technologies are very similar. Data and commands from the controller to memory and back to SLDRAM are transmitted in packets of 4 or 8 messages. Commands, address and control signals are sent over a unidirectional 10-bit command bus. Read and write data is transmitted over a bidirectional 18-bit data bus. Both buses operate at the same frequency. For now, this frequency is still 200 MHz, which, thanks to DDR technology, is equivalent to 400 MHz. The next generations of SLDRAM should operate at frequencies of 400 MHz and higher, that is, provide an effective frequency of more than 800 MHz.

ESDRAM chips. This is a synchronous version of EDRAM that uses the same techniques to reduce access time. A write operation, unlike a read operation, bypasses the cache, which increases ESDRAM performance when resuming reading from a line already in the cache. Thanks to the presence of two banks in the chip, downtime due to preparation for read/write operations is minimized. The disadvantages of the microcircuit under consideration are the same as those of EDRAM - the controller is more complex, since it must read the ability to prepare for reading a new kernel line into the cache memory. In addition, with an arbitrary sequence of addresses, the cache memory is used inefficiently.

End of work -

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Organization of computers and systems

Siberian State Aerospace University.. named after Academician M. F. Reshetnev.. organization of computers and systems..

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Page addressing (PTA) involves dividing the address space into pages. A page is identified by its starting address, which acts as a base. The older part of this

Command loop
The program is being implemented on a von Neumann computer central processor(CPU) through sequential execution of the instructions that form this program. Actions required for sampling (

Main indicators of computers
The use of a specific computer makes sense if its performance corresponds to the performance requirements determined by the requirements for the implementation of specified algorithms. As a basis

i80x86 software architecture
One of the most common general purpose processors on this moment are processors with x86 architecture (Intel IA-32). The forefather of the family of these processors was the i8086 CPU. AND

Code segment
The code segment usually records microprocessor instructions that are executed sequentially one after another. To determine the address of the next command after executing the previous one

Variables in the program
All other segments allocate space for variables used in the program. The division into data segments, stack segment and additional data segment is due to the fact that

Stack segment
To store temporary values for which it is inappropriate to allocate variables, a special memory area called the stack is intended. To address such an area, use seg

Microprocessor i8086
From a programmer's point of view, a microprocessor is represented as a set of registers. Registers are designed to store some data and therefore, in a sense, they correspond

Access to memory cells
As already noted, any microprocessor system must include memory in which programs and the data necessary for their operation are located. Physical and lo

Microprocessor commands
A program running in a microprocessor system is ultimately a set of bytes perceived by the microprocessor as the code of a particular command along with the corresponding

Main groups of commands and their brief characteristics
To simplify the programming process in assembly language, a mnemonic notation of microprocessor commands is used (usually in the form of abbreviations of English words describing actions

Addressing methods in i80x86 architecture
The addressing methods discussed above can be fully applied when writing a program in assembly language. Let's consider methods for implementing the most commonly used methods

Addressing memory cells
In addition to registers and constants, memory cells can be used in commands. Naturally, they can be used both as a source and as a receiver of data. More precisely, the commands use

Direct addressing
With direct addressing, the command specifies the offset, which corresponds to the beginning of the placement of the corresponding operand in memory. By default, when using simplified segment description directives

Indirect addressing
With indirect addressing, the offset of the corresponding operand in the segment is contained in one of the microprocessor registers. Thus, the current contents of the microprocessor register determines the execution

Indirect addressing by base
When using indirect addressing, you can add a constant to the contents of the register. In this case, the executive address is calculated as the sum of the contents of the corresponding register and this constant

Addressing by database with indexing
The i8086 microprocessor can also use a combination of indirect index addressing and base addressing. The executive address of the operand is determined as the sum of three components - the contents of

Laboratory work. i8086 processor software architecture
In the assembly language of the i8086 processor using any convenient package (TASM is recommended), implement the following tasks: 1. Tabulate the function

Structure of computer interconnections
A set of paths that interconnect the main devices of a VM (central processor, memory and input/output modules) forms the structure of the computer’s interconnections.

Tire types
An important criterion that determines the characteristics of a tire can be its intended purpose. Based on this criterion, we can distinguish: · processor-memory buses; · input buses

System bus
To reduce cost, some VMs have a common bus for memory and I/O devices. This type of bus is often called a system bus. The system bus serves for physical and logical

Single bus computer
In single-bus interconnection structures, there is one system bus that provides information exchange between the processor and memory, as well as between the airborne device on the one hand and the processor on the other.

Computer with two types of buses
Although input/output device controllers (IDCs) can be connected directly to the system bus, greater effect is achieved by using one or more I/O buses

Computer with three types of buses
A high-speed expansion bus can be added to the bus system to connect high-speed peripheral devices.

Mechanical aspects
The main bus that connects the devices of a computer is usually located on the so-called backplane or motherboard. The bus is formed by thin parallel copper strips

Electrical aspects
All devices using the bus are electrically connected to its signal lines, which are electrical conductors. By changing the voltage levels on the signal lines,

Bus line distribution
Any transaction on the bus begins with the master device setting address information. The address allows you to select a slave device and establish a connection between it and the master. D

Leased and multiplexed lines
Some VMs combine the address and data lines into a single multiplexed address/data bus. Such a bus operates in time-sharing mode, since the bus cycle is divided into

Priority schemes
Each potential leader is assigned a specific priority level, which can remain constant (static or fixed priority) or vary depending on the priority level.

Arbitration schemes
Arbitration of requests for bus control can be organized in a centralized or decentralized manner. The choice of a specific scheme depends on the performance requirements and

PCI interface
The dominant position in the PC market is sufficient long time occupied by systems based on the PCI bus (Peripheral Component Interconnect - Interaction of peripheral components). This

AGP port
With the widespread introduction of multimedia technologies, the bandwidth of the PCI bus has become insufficient for the productive operation of a video card. In order not to change the existing tire standard

PCI Express
PCI interface Express (originally called 3GIO) uses the PCI concept, but the physical implementation is radically different. At the physical layer, PCI Express represents

Data localization
By data localization we mean the ability to access one of the hosts, as well as address data on it. The host address is usually contained in the address part of the input/output commands

Control and synchronization
The control and synchronization function is that the VVM must coordinate the movement of data between the internal resources of the VM and external devices. When developing systems

Information exchange
The main function of the IIM is to ensure the exchange of information. On the side of the “large” interface, this is an exchange with the CPU, and on the side of the “small” interface, this is an exchange with the computer. In this regard, it is required

Interrupt and exception system in IA-32 architecture
Interrupts and exceptions are events that indicate that certain conditions have occurred in the system or in a currently executing task that require processor intervention.

Advanced Programmable Interrupt Controller (APIC)
IA-32 microprocessors, starting with the Pentium model, contain a built-in advanced programmable interrupt controller (APIC). Built-in APIC is designed for prera registration

Calculation pipeline
Improving the element base no longer leads to a dramatic increase in VM performance. Architectural techniques seem more promising in this regard, including

Synchronous linear conveyors
The efficiency of a synchronous conveyor largely depends on the correct choice of the duration of the clock period Tk. The minimum permissible Tk can be defined as

Conveyor efficiency metrics
To characterize the effect achieved by pipelining calculations, three metrics are usually used: acceleration, efficiency and performance. Under accelerated

Nonlinear conveyors
The pipeline is not always a linear chain of stages. In a number of situations, it turns out to be advantageous when functional blocks are connected to each other not in series, but accordingly

Command pipeline
The idea of a conveyor belt of commands was proposed in 1956 by academician S. A. Lebedev. As you know, a command cycle is a sequence of stages. Having entrusted the implementation of each of

Conflicts in the command pipeline
The number 14 obtained in the example characterizes only the potential performance of the command pipeline. In practice, due to conflict situations arising in the pipeline, achieving such a performance

Methods for solving the conditional jump problem
Despite the importance of the aspect of calculating the execution address of the transition point, the main efforts of VM designers are aimed at solving the problem of conditional transitions, since

Transition Prediction
Transition prediction is today considered one of the most effective ways to deal with management conflicts. The idea is that even before the moment

Static branch prediction
Static branch prediction is carried out on the basis of some a priori information about the program to be executed. The prediction is made at the stage of program compilation and

Dynamic branch prediction
In dynamic strategies, the decision about the most likely outcome of the command is made during calculations, based on information about previous transitions (transition history), collected

Superpipeline processors
The efficiency of a conveyor is directly dependent on the frequency with which processing objects are supplied to its input. You can achieve an n-fold increase in the rate of operation of the conveyor

Full and reduced instruction set architectures
Modern programming technology is focused on high-level languages (HLL), the main task of which is to facilitate the process of writing programs. More than 90% of the entire program process

Main features of RISC architecture
The main efforts in RISC architecture aimed at building the most efficient command pipeline, that is, one where all commands are retrieved from memory and sent to the CPU for processing

Advantages and Disadvantages of RISC
Comparing the advantages and disadvantages of CISC and RISC, it is impossible to make an unambiguous conclusion about the undeniable advantage of one architecture over the other. For certain areas of use of VM l

Superscalar processors
Since the possibilities for improving the element base have already been practically exhausted, further increasing the performance of VMs lies in the plane of architectural solutions. As already about

Laboratory work. VM execution devices
Counters. A counter is a device whose output signals display the number of pulses received at the counting input. A JK flip-flop can serve as an example of a simple

Characteristics of memory systems
The list of main characteristics that must be taken into account when considering a specific type of memory includes: · location; · capacity; · unit

Hierarchy of storage devices
Memory is often called the “bottleneck” of von Neumann VMs due to its serious performance lag behind processors, and this gap is steadily increasing. So, if

Main memory
Main memory (RAM) is the only type of memory that the CPU can access directly (except for CPU registers). Information storing

Block organization of main memory
The main memory capacity of modern VMs is too large to be implemented on a single integrated circuit (IC). The need to combine several ICs

Organization of memory chips
Integrated circuits (ICs) of memory are organized in the form of a matrix of cells, each of which, depending on the capacity of the IC, consists of one or more storage elements (SE)

Synchronous and asynchronous storage devices
As a first criterion by which main memory storage devices can be classified, consider the synchronization method. From these positions known types Memory subsection

Random access storage devices
Most of the currently used types of RAM chips are not able to store data without an external source of energy, that is, they are volatile (vo

Static and dynamic RAM
In static RAM, the storage element can store recorded information indefinitely (subject to supply voltage). Dynamic storage element

Static random access memories
Let us recall that the role of a storage element in static RAM is played by a trigger. Static RAM is currently the fastest, but also the most expensive type of RAM.

Laboratory work. Advanced work with memory and transfer of control in the program
Implement the following programs in assembly language of the i8086 microprocessor using the call and ret control transfer commands: 1. Define the cut

Magnetic disks
Information in magnetic disk storage (MD) is stored on flat metal or plastic plates (disks) coated with magnetic material. Data is written to and read from

Data organization and formatting
The data on the disk is organized into a series of concentric circles called tracks (Figure 72). Each of them has the same width as the head. Adjacent paths are separated by gaps. This

Internal structure of disk systems
Fixed-head memories have one read/write head per track. The heads are mounted on a rigid arm that crosses all the tracks of the disk. On disk

Redundant Array Concept
Magnetic disks being the basis external memory any VM, at the same time remain one of the “bottlenecks” due to the relatively high cost, insufficient performance and fault

Improving disk subsystem performance
Increasing the performance of the disk subsystem in RAID is achieved using a technique called striping. It is based on data partitioning and di

Improving the fault tolerance of the disk subsystem
One of the goals of the RAID concept was the ability to detect and correct errors that arise from disk failures or failures. This is achieved due to redundant disk space

RAID level 0
RAID level 0, strictly speaking, is not a full-fledged member of the RAID family, since this scheme does not contain redundancy and is aimed only at improving performance in a limited way.

RAID Level 1
RAID 1 achieves redundancy by duplicating data. In principle, source data and their copies can be placed arbitrarily on a disk array, the main thing is that they are found

RAID Level 2
RAID 2 systems use parallel access technology, where all disks are simultaneously involved in executing each I/O request. Usually the spindles of all disks are synchronized

RAID Level 3
RAID 3 is organized similarly to RAID2. The difference is that RAID 3 only requires one additional disk - a parity disk, no matter how large the disk array is (p

RAID Level 4
In its idea and technique for generating redundant information, RAID 4 is identical to RAID 3, only the size of the stripes in RAID 4 is much larger (usually one or two physical blocks on the disk). Gla

RAID Level 5
RAID 5 has a structure similar to RAID 4. The difference is that RAID 5 does not have a separate disk to store parity stripes, but rather spreads them across all disks. Typical

RAID Level 6
RAID 6 is very similar to RAID 5. Data is also split into block-sized stripes and distributed across all drives in the array. Likewise, the parity stripes are distributed across different disks.

RAID level 7
RAID 7, patented by Storage Computer Corporation, combines an array of asynchronously operating disks and cache memory managed by the array controller's built-in operating system.

RAID level 10
This scheme identical to RAID 0, but unlike it the role separate disks perform disk arrays, built according to the RAID 1 scheme (Fig. 83). Thus, in RAID 10 soche

Features of the implementation of RAID systems
RAID arrays can be implemented in software, hardware, or a combination of software and hardware. When implemented in software, conventional disk drives are used.

Optical memory
In 1983, the first digital audio system based on compact discs (CD - compact disk) was introduced. A compact disc is a single-sided disc capable of storing more than 60 minutes of

Levels of parallelism
Methods and means for implementing parallelism depend on the level at which it should be provided. Typically, the following levels of parallelism are distinguished: · Job level. Nesk

Program level parallelism
It makes sense to talk about parallelism at the program level in two cases. Firstly, when a program can have independent sections that can be executed in parallel

Instruction level parallelism
Command-level concurrency occurs when the processing of multiple commands or the execution of different steps of the same command may overlap in time. Computing developers

Program Concurrency Profile
The number of processors of a multiprocessor system participating in parallel in the execution of the program at each moment of time t is determined by the concept of the degree of parallelism D(t) (

Let's consider the parallel execution of a program with the following characteristics: · O(n) - the total number of operations (commands) performed on an n-processor system;

Amdahl's Law
By purchasing a parallel computing system to solve his problem, the user expects a significant increase in computing speed due to the distribution of computing power

Gustafson's Law
A certain amount of optimism in the assessment given by Amdahl's law comes from research conducted by the already mentioned John Gustafson from NASA Ames Research. Solving on a computer system

Cache coherence in SMP systems
The memory bandwidth requirements of modern processors can be significantly reduced by using large multi-level caches. Then if these requirements

Cache coherence in MPP systems
There are two different ways to build large-scale distributed memory systems. The simplest way is to eliminate the hardware mechanisms that provide

Organization of interrupts in multiprocessor systems
Let's consider the implementation of interrupts in the simplest symmetric multiprocessor systems, which use several processors connected by a common bus. Each processor

Conclusion
It is not possible to cover all aspects of the structure and organization of computers in one publication (and even within one course). Knowledge in this area of human activity

Bibliography
1. Aven, O.I. Assessing the quality and optimization of computer systems / O.I. Aven, N. Ya. Turin, A. Ya. Kogan. – M.: Nauka, 1982. – 464 p. 2. Voevodin, V.V. Parallel computing

Over time, developers have created various types of memory. They had different characteristics and used different technical solutions. The main driving force behind the development of memory was the development of computers and central processing units. There was a constant need to increase the speed and amount of RAM.

Page memory

Page mode DRAM (PM DRAM) was one of the first types of computer RAM produced. Memory of this type was produced in the early 1990s, but with the increase in processor performance and resource intensity of applications, it was necessary to increase not only the amount of memory, but also the speed of its operation.

Fast page memory

Fast page memory (eng. fast page mode DRAM, FPM DRAM) appeared in 1995. The memory did not undergo any fundamentally new changes, and the increase in operating speed was achieved by increasing the load on the memory hardware. This type of memory was mainly used for computers with Intel 80486 processors or similar processors from other companies. The memory could operate at frequencies of 25 and 33 MHz with full access times of 70 and 60 ns and duty cycle times of 40 and 35 ns, respectively.

EDO DRAM -- memory with enhanced output

With the advent of Intel Pentium processors, FPM DRAM memory turned out to be completely ineffective. Therefore, the next step was memory with an improved output (extended data out DRAM, EDO DRAM). This memory appeared on the market in 1996 and began to be actively used on computers with Intel Pentium processors and higher. Its performance was 10-15% higher compared to FPM DRAM type memory. Her operating frequency was 40 and 50 MHz, respectively, the full access time was 60 and 50 ns, and the duty cycle time was 25 and 20 ns. This memory contains a data latch for the output data, which provides some pipelining for improved read performance.

SDRAM -- synchronous DRAM

Due to the release of new processors and a gradual increase in the system bus frequency, the stability of EDO DRAM memory began to noticeably decrease. It was replaced by synchronous memory (eng. synchronous DRAM, SDRAM). New features of this type of memory were the use of a clock generator to synchronize all signals and the use of pipelined information processing. The memory also worked reliably at higher system bus frequencies (100 MHz and higher).

If for FPM and EDO memory the reading time of the first cell in the chain (access time) is indicated, then for SDRAM the reading time of subsequent cells is indicated. A chain is several consecutive cells. It takes quite a lot of time to read the first cell (60-70 ns), regardless of the type of memory, but the time to read subsequent ones greatly depends on the type. The operating frequencies of this type of memory could be 66, 100 or 133 MHz, the full access time was 40 and 30 ns, and the duty cycle time was 10 and 7.5 ns.

Virtual Channel Memory (VCM) technology was used with this type of memory. VCM uses a virtual channel architecture that allows data to be transferred more flexibly and efficiently using on-chip register channels. This architecture integrated into SDRAM. VCM, in addition high speed data transfer, was compatible with existing SDRAM, which made it possible to upgrade the system without significant costs and modifications. This solution has found support from some chipset manufacturers.

Enhanced SDRAM (ESDRAM)

To overcome some of the signal latency problems inherent in standard DRAM memory, it was decided to embed a small amount of SRAM on the chip, that is, create an on-chip cache.

ESDRAM is essentially SDRAM with a small amount of SRAM. With low latency and burst operation, frequencies up to 200 MHz are achieved. As with external cache memory, the SRAM cache is designed to store and retrieve the most frequently accessed data. Hence the reduction in data access time of slow DRAM.

One such solution was ESDRAM from Ramtron International Corporation.

Batch EDO RAM

EDO RAM (burst extended data output DRAM, BEDO DRAM) has become a cheap alternative to SDRAM. Based on EDO DRAM, its key feature was block-by-block technology (a block of data was read in one clock cycle), which made it faster than SDRAM. However, the inability to operate at a system bus frequency of more than 66 MHz did not allow this type of memory to become popular.

A special type of RAM - Video RAM (VRAM) - was developed based on SDRAM memory for use in video cards. It allowed for a continuous flow of data during the image update process, which was necessary to realize high quality images. Based on memory type VRAM, a memory specification like Windows RAM(WRAM), sometimes mistakenly associated with operating systems Windows family. Its performance is 25% higher than the original SDRAM, thanks to some technical changes.

Compared to conventional SDRAM, double data rate SDRAM (DDR SDRAM or SDRAM II) doubled the bandwidth. Initially, this type of memory was used in video cards, but later support for DDR SDRAM appeared on the chipset side.

All previous DRAMs had separate address, data, and control lines, which imposed limitations on the speed of the devices. To overcome this limitation, some technology solutions have implemented all signals on a single bus. Two of these solutions are DRDRAM and SLDRAM technologies. They have received the most popularity and deserve attention. The SLDRAM standard is open and, like previous technology, SLDRAM uses both clock edges. As for the interface, SLDRAM adopts a protocol called SynchLink Interface and aims to operate at 400 MHz.

DDR SDRAM memory operates at frequencies of 100, 133, 166 and 200 MHz, its full access time is 30 and 22.5 ns, and its duty cycle time is 5, 3.75, 3 and 2.5 ns.

Since the clock frequency ranges from 100 to 200 MHz, and data is transmitted at 2 bits per clock pulse, both on the edge and on the fall of the clock pulse, the effective data transmission frequency lies in the range from 200 to 400 MHz. Such memory modules are designated DDR200, DDR266, DDR333, DDR400.

Direct RDRAM or Direct Rambus DRAM

The RDRAM memory type is developed by Rambus. The high performance of this memory is achieved by a number of features not found in other types of memory. The initial very high cost of RDRAM memory led to the fact that manufacturers of powerful computers preferred less powerful, but cheaper DDR memory SDRAM. Memory operating frequencies are 400, 600 and 800 MHz, full access time is up to 30 ns, duty cycle time is up to 2.5 ns.

Structurally new type DDR2 SDRAM was released in 2004. Based on DDR SDRAM technology, this type of memory, due to technical changes, shows higher performance and is intended for use on modern computers. The memory can operate at bus clock speeds of 200, 266, 333, 337, 400, 533, 575 and 600 MHz. In this case, the effective data transmission frequency will be 400, 533, 667, 675, 800, 1066, 1150 and 1200 MHz, respectively. Some manufacturers of memory modules, in addition to standard frequencies, also produce samples operating at non-standard (intermediate) frequencies. They are intended for use in overclocked systems where frequency headroom is required. Full access time -- 25, 11.25, 9, 7.5 ns or less. Duty cycle time - from 5 to 1.67 ns.

This type of memory is based on DDR2 SDRAM technologies with twice the data transfer frequency on the memory bus. It features lower power consumption compared to its predecessors. The bandwidth frequency ranges from 800 to 2400 MHz (the frequency record is more than 3000 MHz), which provides greater throughput compared to all predecessors.

DRAM memory designs

Rice. 4. Various cases DRAM. From top to bottom: DIP, SIPP, SIMM (30-pin), SIMM (72-pin), DIMM (168-pin), DIMM (184-pin, DDR)

Fig.5.

Rice. 6. DDR2 module in 204-pin SO-DIMM package

DRAM memory is structurally implemented both in the form of separate microcircuits in packages such as DIP, SOIC, BGA, and in the form of memory modules of the type: SIPP, SIMM, DIMM, RIMM.

Initially, memory chips were produced in DIP-type packages (for example, the K565RUxx series), then they began to be produced in more technologically advanced packages for use in modules.

Many SIMM modules and the vast majority of DIMMs had SPD (Serial Presence Detect) installed - a small EEPROM memory chip that stores module parameters (capacity, type, operating voltage, number of banks, access time, etc.), which were available in software as equipment in which the module was installed (used for auto-configuring parameters), and to users and manufacturers.

SIPP modules

SIPP (Single In-line Pin Package) type modules are rectangular boards with contacts in the form of a series of small pins. This type of design is practically no longer used, since it was later replaced by SIMM-type modules.

SIMM modules

SIMM (Single In-line Memory Module) type modules are long rectangular boards with a number of pads along one of its sides. The modules are fixed in the connection connector (socket) using latches, by installing the board at a certain angle and pressing it until it is brought to a vertical position. Modules of 4, 8, 16, 32, 64, 128 MB were produced.

The most common are 30- and 72-pin SIMMs.

DIMMs

Modules of the DIMM type (Dual In-line Memory Module) are long rectangular boards with rows of contact pads along both sides, installed vertically into the connection connector and secured at both ends with latches. Memory chips on them can be placed on one or both sides of the board.

SDRAM memory modules are most common in the form of 168-pin DIMM modules, DDR SDRAM memory modules are in the form of 184-pin modules, and DDR2, DDR3 and FB-DIMM SDRAM memory modules are 240-pin modules.

SO-DIMMs

For portable and compact devices (Mini-ITX form factor motherboards, laptops, notebooks, tablets, etc.), as well as printers, network and telecommunications equipment, etc., structurally reduced DRAM modules (both SDRAM and DDR SDRAM) -- SO-DIMM (Small outline DIMM) -- analogues of DIMM modules in a compact design to save space.

RIMM modules

Modules of the RIMM type (Rambus In-line Memory Module) are less common; they come with RDRAM type memory. They are represented by 168- and 184-pin varieties, and on the motherboard such modules must be installed only in pairs, otherwise special plug modules are installed in empty connectors (this is due to the design features of such modules). There are also 242-pin PC1066 RDRAM RIMM 4200 modules, which are not compatible with 184-pin connectors, and a smaller version of RIMM - SO-RIMM, which are used in portable devices.

Dynamic memory of any type, unlike static memory, even when supply voltage is applied, does not have the ability to store its information indefinitely. The state of a dynamic memory unit cell is determined by the presence or absence of charge on the capacitor, and this charge is subject to leakage. Therefore, in order to save data in dynamic memory, its cells must be periodically recharged, which is the essence of the regeneration process. Below is how this happens.
When a read operation is performed, regeneration is performed automatically. The data received at the signal amplifier is immediately written back. It is believed that such an algorithm can reduce the number of required regenerations and increase performance. But this is absolutely not true! Whether information is read from memory or not, the regeneration “frequency” does not change. It is either not regulated at all (there are no corresponding options in the "BIOS Setup"), or is strictly fixed after the appropriate settings.

Three different data regeneration methods are possible.

Regeneration with one RAS (RAS Only Refresh - ROR). This method was used in the first DRAM chips. The address of the row being regenerated is transferred to the address bus and the RAS signal is issued (just like when reading or writing). In this case, a row of cells is selected, and the data from them is sent to the internal circuits of the microcircuit, and then written back. Since there is no further CAS signal, the read/write cycle does not begin. The address of the next row is then transmitted, and so on, until the entire memory matrix has been traversed, after which the regeneration cycle is repeated. The disadvantages of this method include the fact that the address bus is occupied, and at the time of regeneration, access to other computer subsystems is blocked.
CAS Before RAS (CAS Before RAS - CBR) is the standard regeneration method. In a normal read/write cycle, RAS always arrives first, followed by CAS. If CAS arrives before RAS, then a special regeneration cycle begins - CBR. In this case, the row address is not transmitted, and the chip uses its internal counter, the contents of which are increased by 1 with each CBR cycle (the so-called row address increment). This mode allows you to regenerate memory without occupying the address bus, which is certainly more economical.
Automatic memory regeneration (Self Refresh - SR, or self-regeneration). This method is usually used in power saving mode, when the system goes into a "sleep" state ("suspend") and the clock oscillator stops working. In this state, updating the memory using the methods described above is impossible (there are simply no signal sources), and the memory chip performs regeneration on its own. It starts its own generator, which clocks the internal regeneration circuits. This memory technology was introduced with the advent of EDO DRAM. It should be noted that in sleep mode the memory consumes very little current.
In the classic PC AT implementation, requests for DRAM regeneration were generated by channel 1 of the 8254 system timer. A trigger is connected to its output, operating in counting mode and changing its state to the opposite one with each request. The state of this flip-flop can be read programmatically via bit 4 of port 61h. Examination Refresh Toggle was to check the fact that this trigger switches at a given frequency. But over time, other memory regeneration algorithms began to be used (as described above), and despite the fact that Refresh Toggle is retained for compatibility; it can no longer be used to check the generation of regeneration requests. Regeneration cycles are performed by the regeneration controller included in the chipset, which must receive highway control every 15.6 μs to perform its task. During the regeneration cycle, one of N memory cells is read.

Burst Refresh

- (batch regeneration). As a rule, the interpretation of this option in the literature is erroneous. When the option is enabled ("Enabled"), requests for regeneration are collected into a single package, and such packaging can, in some cases, ensure the accumulation of requests across the entire volume of rows in memory. This method leads to a significant increase in productivity, but there are also back side. For fairly long periods of time and constantly, the memory bus is captured, which leads to blocking access to it by the processor or other devices.
The option may be called "DRAM Burst Refresh".

CAS Before RAS Refresh

A memory regeneration method where the CAS signal is set before the RAS signal. Unlike the standard regeneration method, this method does not require enumeration of row addresses from outside the memory chips - an internal address counter is used. However, this regeneration method must be supported by memory chips. If earlier you could come across phrases that most memory modules support this regeneration method, now this is already standard hardware solution. Using this method can significantly reduce the energy consumed by memory modules. Can take values:
"Enabled" - allowed,
"Disabled" - prohibited.
The option may be called "CAS Before RAS".

CAS-to-RAS Refresh Delay

This option can operate when the previous (or similar) option is enabled, since in this case the delay time between strobe signals is set (in system bus clock cycles). Naturally, setting a lower value leads to a decrease in the time spent on regeneration. A larger value increases reliability, i.e. reliability of data in memory. The optimal option for a given system is selected experimentally. Can take values: "1T", "2T" (default).

Concurrent Refresh

- (parallel or competing regeneration). When this option is enabled, both the regeneration hardware and the CPU have simultaneous memory access. In this case, the processor will not need to wait until regeneration occurs. When setting the option to "Disabled", the processor will have to wait until the regeneration circuit finishes working. Naturally, enabling the option improves system performance.

Decoupled Refresh

- (separate regeneration). Since the ISA bus has a low operating speed, enabling this option (“Enabled”) will allow the chipset to separate regeneration for the main memory and the ISA bus. In this case, the regeneration process for the ISA bus can be completed while the processor is executing other instructions. Using this option significantly increases the performance of the entire system. This option played a significant role in the days of 486 cars.
But a problem that could arise was that some expansion cards (usually video cards) required the attention of the processor during the initial bus regeneration cycle. Naturally, this could lead to unwanted failure situations. Disabling the option might also be necessary if, when working with high-resolution graphics modes, some symbols or “snow” appeared on the monitor screen. In this case, it was necessary to disable such a method of working with memory as “Memory Relocation” (see above). The above was typical, for example, for video cards on the S3 801 chip (such as SPEA V7 Mirage), working in conjunction with some controller cards manufactured by Adaptec with expanded ROM memory necessary to service hard drives with a capacity of over 1 GB.
The option may be called "Decoupled Refresh Option".

Distributed Refresh

- (distributed regeneration). It is not entirely clear what is “hidden” under this option, although there is an assumption that it is an analogue of “separate regeneration”. At one time, this option could be found in systems based on chipsets from VIA Technologies. Option values: "Disabled" and "Enabled".

DRAM Ahead Refresh

An option that allows you to enable ("Enabled") the "anticipation" mode for the regeneration cycle. The essence of this "foresight" will become more clear from the following option, which becomes active when the permission is enabled.
x DRAM Ahead Refresh Timing
- this option essentially allows you to “push back” the start of the regeneration cycle by 10 or 40 system clock cycles. Small, but still an increase in performance. Such unique options were implemented in systems based on the SIS540 kit and have never been seen anywhere else.

DRAM Burst at 4 Refresh

This option is also related to batch regeneration, but its essence is different. Enabling the option (“Enabled”) enables regeneration of 4 lines per batch. This method significantly improves productivity. In this case, the bus is released much faster than in the case of the "Burst Refresh" option.

DRAM CAS# Precharge

- (CAS pre-charge time). This function is used if the system has synchronous dynamic memory, and with its help it sets (in system bus clocks) the time for generating the CAS signal (CAS charge accumulation) before the start of the memory regeneration cycle (see below for additional information "DRAM RAS# Precharge Time" ). Decreasing this value increases performance, but there may be problems with system stability if at the same time the "borderline" values for the RAS strobe are set. If the value (time) is set too low, the regeneration may also not be completed, which will ultimately lead to the loss of data in memory.
The option may have the following names: "CAS# Precharge", "CAS# Precharge Time", "FPM CAS# Precharge", "FPM DRAM CAS Precharge", "EDO/FPM CAS Precharge Time", "EDO CAS# Precharge", "EDO DRAM CAS Precharge".
All of the listed options do not differ in a wide variety of meanings. "1T", "2T" or this series: "1T", "1T/2T", "2T". The "CAS Precharge Period" option added some variety: "1T", "2T", "3T", "4T".

DRAM RAS Only Refresh

Enable/disable DRAM refresh method, alternative method"CAS-before-RAS". If the BIOS contains other options for memory regeneration, then this option must be disabled. Otherwise you will have to use this outdated memory upgrade method.

DRAM RAS# Precharge Time

- (RAS pre-charge time). This function is used when the system has synchronous dynamic memory and it allows you to set the time (in system bus clocks) for generating the RAS signal (sometimes referred to as RAS charge accumulation) before the memory regeneration cycle begins. In effect, this sets a minimum interval between two consecutive read or write cycles. Decreasing this value increases performance. But if the time is set insufficiently, the regeneration may be incomplete, which will ultimately lead to the loss of data in memory. Naturally, an increase in the frequency at which the memory operates is followed by the choice of a higher value, which is important when overclocking the memory. Possible values can be presented in various forms: as digital values - “3”, “4”, etc.; indicating system clocks - "3 Clocks" or "1T". And the generalized range of values has the following form: 0T, 1T, 2T, 3T, 4T, 5T, 6T, although in each specific option 2-4 values can be presented.
The option can have many names: "DRAM RAS# Precharge Period", "RAS# Precharge Time", "RAS Precharge Timing", "RAS# Precharge Period", "FPM DRAM RAS# Precharge", "FPM RAS Precharge", "RAS # Precharge", "DRAM RAS Precharge", "EDO RAS Precharge", "EDO RAS# Precharge Time", "EDO RAS Precharge Timing", "FPM/EDO RAS# Precharge Time", "EDO/FPM RAS Precharge Time".
As you can see, the option has not lost its relevance with the advent of EDO memory and, interestingly, then also BEDO and SDRAM modules, since this parameter is one of the most important characteristics memory chips: "BEDO RAS Precharge", "SDRAM RAS Precharge Time".
True, in addition to the usual parameters like “3T” or “2 Clks” (these values are typical for SDRAM modules) in various BIOS versions new types of values began to appear, such as: “Same as FPM” and “FPM-1T”, “Fast” and “Normal”, “Fast” and “Slow”. For the last pair of parameters, “Slow” (slowly) is equivalent to an increase in the number of clock cycles, which increases the stability of the system, so the “Fast” value should be set if you are confident in the quality of the memory modules. As for the first pair, for options like “FPM DRAM RAS# Precharge” a number of values could look like: 2T, 3T, 4T, 5T, 6T, and hence a possible result for SDRAM memory, although not at all obvious.
It is also quite possible that the BIOS version provides the ability to set some parameters for each memory bank separately. Since we are talking about “precharge” for the RAS# strobe, the option(s!) can be called “Bank 0&1 (2&3)(4&5): EDO/SDRAM Precharge” with the values: “3T/2T”, “4T/3T” .
"AMI BIOS" offered an additional value of "Auto" for its "SDRAM RAS# Precharge" option. True, one of the options for the “SDRAM RAS Precharge” option also introduced the “Disabled”/“Enabled” values. You can disable the option only if you are absolutely confident in the memory modules, otherwise troubles cannot be avoided. Since we touched on the ability to disable/enable the precharge mechanism, we should also note the ability to enable (“Enabled”) precharge optimization - “SDRAM: Optimal RAS# Prech.”.
There are a couple of important things to note about this option(s!). This option should not be confused with options like "Refresh RAS Active Time", which are responsible for the duration of the RAS# signal. In our case, we are talking about a preparatory process. And second! It would be absolutely correct to place this option in the section devoted to standard memory optimization (see below). The procedures for setting the RAS# signal during both regeneration and read/write operations are identical.
To complete the above, the option is "RAS# Precharge/Refresh" with the values "3T/4T" and "4T/5T". This option sets both the preparatory phase time and the total active time of the RAS# signal for the regeneration cycle.

DRAM Refresh Method

Option to set the regeneration method. The option may also be called "Refresh Type", "DRAM Refresh Type", "DRAM Refresh Mode" or "Refresh Type Select". For any variations, the option, as a rule, contains only two parameters among the possible parameters. We present the entire possible series: “CAS before RAS” (or “CAS-RAS”), “RAS only”, “RAS# Before CAS#”, “Normal”, “Hidden”.

DRAM Refresh Period

Setting the period (repetition frequency) required for memory regeneration, in accordance with the specification of the memory modules. In the latest BIOS versions, this option may not be present, although its presence in a modern system still allows you to optimize the regeneration process. Previously, this option offered the user wide scope for creativity: depending on the BIOS version and its manufacturer, chipset, and memory modules. The option could also be called "Refresh Cycle Time (us)", "DRAM Refresh Cycle Time", "Memory Refresh Rate", "DRAM Refresh Rate Select", "DRAM Refresh Rate", "SDRAM Refresh Rate" or simply "DRAM Refresh". Here is a partial list of values that the user might encounter:
“For 50 MHz Bus”, “For 60 MHz Bus”, “For 66 MHz Bus”, “Disabled” (this unusual option was found in the system on i430FX),
"50/66 MHz", "60/60 MHz", "66/66 MHz",
"15 us", "30 us", "60 us", "120 us",
"Disabled" (or "No Refresh"), "15.6 us", "31.2 us", "62.4 us", "124.8 us", "249.6 us",
"15.6 us", "31.2 us", "62.4 us", "125 us", "250 us",
"15.6 us", "62.4 us", "124.8 us", "187.2 us",
"1040 Clocks", "1300 Clocks",
"15.6 us", "7.9 us", "FR 128 CLKs" (it is clear that we are talking about frequency - "frequency"),
"Disabled", "Normal",
"Fast", "Slow",
"Faster", "Slower",
"Disabled" (standard 15.6 µs is set), "Enabled" (corresponds to doubling the frequency).
It remains to be noted that the less frequently memory is regenerated, the more efficiently the system operates. But if there are clearly observed violations in the operation of the system, then the update frequency must be increased. The "Disabled" value that appears in some versions should not be used. Otherwise, you should expect loss of information in memory. And finally, if the user sees on the screen in front of him a whole series of values for selection, this may mean that the chipset includes a special configuration register in which three digits (or less) are “given” to possible combinations of the set frequency.
In addition to the above, let's look at some more options and the chipsets for which they were implemented:
"DRAM Refresh Ratery Time" (SIS530) - "15.6 us", "7.8 us", "3.9 us",
"Refresh Rate" (AMD751) - "20.4 us", "15.3 us", "10.2 us", "5.1 us".
The "Refresh Mode Select" option, despite some inconsistency in the name, suggested the values "7.8?sec", "15.6?sec", "64?sec", and the "Refresh Interval" option - "7.8?sec", "15.6?sec" sec", "31.2 ?sec", "64 ?sec", "128 ?sec".
This is where, on the one hand, an imaginary discrepancy may arise, and on the other, some misunderstanding of the essence of the options presented. After all, the names of the options include “frequency”, “period”, “interval”, and “cycle time”. Therefore, further clarification is required.
It is clear that it is impossible to regenerate all dynamic memory at the same time. It is also acceptable to talk about row-by-row regeneration of the memory matrix (see above for this). Then you can introduce two concepts at once. The first is the time interval between regeneration, for example, of adjacent lines. The second is the time of the full regeneration cycle, i.e. the time after which the conditional starting line will need to be regenerated again. A "regular" memory chip contains 4096 lines. It can be stated that the total regeneration cycle time is 64 ms (one of the JEDEC standards). And then the mentioned regeneration interval (period) is:
64000: 4096 = 15.6 ?sec.
This means that every 15.6 µs the memory controller initiates a refresh cycle for a single memory line. And this value is typical for the same DIMM modules with a capacity of 128 Mbit or less. If we are talking about modules with a capacity of 256 Mbit or more, then the number of lines will be 8192 and the regeneration interval will be 7.8?sec, due to the preservation of the total cycle time of 64 ms. If the system uses modules of different capacities, then the regeneration time characteristic is set according to the module of the larger capacity, i.e. with a higher frequency.
It should be noted that previously used memory modules in many cases made it possible to lengthen the regeneration cycle, i.e. increase its interval, thereby slightly increasing system performance.
And, of course, the picture would be incomplete if we did not remember RAMBUS DRAM. We will not dwell in detail on the architecture of this type of memory; we will only recall that the structure and organization of memory banks is multi-channel in nature. Moreover, each data channel is a bus only one (!) byte wide. But thanks to a high-performance pipeline, a high-speed internal backbone synchronized by its own clock generator, the memory bus bandwidth has already been increased to 3.2 GB/sec. Well, now the option is “RDRAM Refresh Rate, Channel N”, and its values: “No refresh”, “1.95 us”, “3.9 us”, “7.8 us”.

DRAM Refresh Queue

When enabled, this option allows more than effective method memory updates. The fact is that the chipset is capable of generating a sequence of several memory update requests until the processor bus is ready to perform the next operation. We are talking here about using the pipeline mode for memory regeneration requests. "Enabled" allows typically 4 memory regeneration requests to be queued. Setting it to "Disabled" means disabling pipelining, which naturally reduces efficiency and causes all regeneration cycles to be carried out either by request priority or in accordance with the methods outlined in other options.
This mode must always be on. "Enabled" is also set by default. One condition! Installed modules Memory must support this property; most modern memory types support this method. Moreover! The use of such an effective regeneration method depends both on the implementation of such functions by the chipset and on the BIOS version. In such an explicit, “user” form, this option was found in the “AMI BIOS”.
The option may also be called "DRAM Refresh Queing".

DRAM Refresh Queue Depth

This option allows you to set the degree ("depth") of pipelining, i.e. number of possible conveyor steps. The higher this number, the more regeneration requests are currently being processed. Possible values, which naturally depend on the above implementations and capabilities, are:
"0" (equivalent to "Disabled"), "4", "8", "12" (default).
The option may also be called "Refresh Queue Depth".

Extended Refresh

- (extended regeneration). The introduction (at one time) of this option in the BIOS implied the use of special EDO chips. Regeneration of the contents of EDO DRAM cells began to occur every 125 μs, and not every 15.6 μs, as with standard regeneration. This slightly increased the overall memory performance.

Fast DRAM Refresh

- (fast DRAM regeneration). The memory controller provides two modes of memory regeneration: standard (Normal) and hidden (Hidden). In each mode, the CAS strobe is set before the RAS signal, however, in the “Normal” mode, an additional processor cycle is allocated for each strobe pulse. This is an old method of updating memory, and therefore it makes sense to set the value of this parameter to "Hidden", which provides both increased speed and greater efficiency (see below), also due to the fact that the CAS strobe may not be set - it may be "hidden".

Hidden Refresh

- (hidden regeneration). When set to "Disabled", memory is regenerated using the IBM AT methodology, using processor cycles for each regeneration. When the "Hidden Refresh" option is set to "Enabled", the memory controller "seeks" the most convenient moment to refresh, regardless of CPU cycles. In this case, regeneration occurs simultaneously with normal memory access. The memory regeneration algorithm is multivariate: regeneration cycles are allowed in memory banks not currently used by the central processor, instead of or together with normal regeneration cycles performed every time (every 15 ms) at a certain interrupt (DRQ0), caused by a timer and initiated by the circuit regeneration.
Regeneration requires up to 4 ms each time. During these 4 ms, one regeneration cycle approximately every 16 μs regenerates 256 lines of memory (characteristics for low-capacity memory modules are given here and above). Each regeneration cycle takes the same or slightly less time than one memory read cycle, because The CAS signal is not required for regeneration.
"Hidden refresh" is characterized by maximum speed and efficiency, the least disruption to system activity and the least loss of performance, also allowing you to maintain the state of memory while the system is in "suspend" mode. This mode is faster than "Burst Refresh". But the presence of this function in the BIOS does not mean its implementation. After setting the option to "Enabled", you should carefully check the functionality of the computer. Some memory modules allow you to use "Hidden Refresh", some do not. In most cases it is recommended to set it to "Enabled".

Hi-Speed Refresh

With this option, the chipset will regenerate the main memory faster. True, the effect of this setting is much less than that of turning on "Slow Refresh". The latter regeneration mode is preferable. In addition, this function is not supported by all memory chips.

ISA Refresh

Option to enable/disable memory regeneration for the ISA bus. This option was no longer seen in this form even in the last years of the ISA bus's existence.

ISA Refresh Period

Setting the frequency for ISA bus regeneration. Possible range of values: "15 us", "30 us", "60 us", "120 us".

ISA Refresh Type

Option to set the memory regeneration method for the ISA bus. Possible parameter values: "Normal" and "Hidden". A similar option called "ISA Bus Refresh Mode" could offer other values: "Slow" and "Fast".

PCI-to-DRAM RAS# Precharge

The topic of “precharging” has already been sufficiently mastered by us, so we just need to say briefly about the purpose of this option - setting the “precharging” time of the RAS# strobe during PCI bus write cycles to the main dynamic memory. Option values: "2T", "3T".

RAS Precharge @Access End

When "Enabled" is selected, the RAS# strobe remains active at the end of the "precharge" process. If set to "Disabled", RAS# is placed in a passive state (high level).

RAS Timeout

When set to "Disabled", the dynamic memory regeneration cycle is performed in standard mode, i.e. every 15.6 µs. An additional memory regeneration cycle is inserted when "Enabled" is selected.

Ref/Act Command Delay

- (set the delay for the read/write cycle). The parameter selects the delay time between the end of the regeneration cycle and the beginning of the read or write cycle. The option can take the following values: "5T", "6T" (default), "7T", "8T".
The system on the SIS530 set offered an option called "DRAM Refresh/Active Delay" with slightly more conservative values: "9T", "8T", "7T", "6T". A more advanced chipset (SIS540) has already introduced two options: "DRAM REF/ACT Delay" ("10T", "9T") and "DRAM ACT/REF Delay" ("10T", "9T", "8T"). It is clear that the last option is intended to select the delay for the regeneration mode after the end of the read/write cycle. Smaller values are, of course, more preferable. This option is no longer found in modern systems.

Refresh During PCI Cycles

An option that allows/prohibits memory regeneration during read/write cycles on the PCI bus. Can take values:
"Enabled" - allowed,
"Disabled" - prohibited.

Refresh RAS# Assertion

- (setting the period of RAS signal activity). This parameter sets the duration of the RAS signal (in system bus clocks) for the regeneration cycle. A lower value improves system performance. But since the accepted values are determined by the quality of the memory and the chipset, their installation must be approached with caution. Can take the following values: "4T" (or "4 Clks"), "5T" (or "5 Clks"). There may be other meanings.
The option may also be called "Refresh Assertion", "Refresh RAS Active Time" or "RAS Pulse Width Refresh".

Refresh Value

This option set the regeneration frequency multiplier. A lower value increased system performance by reducing the regeneration frequency. But at the same time also best option could only be achieved by experimental verification. The option values could be selected from the following range: 1, 2, 4, 8, 16. Sometimes the value 0.5 could be found. This option has not been available for a long time.
The option may be called "Refresh Divider".

Refresh When CPU Hold

A rather outdated option that suggested regeneration ("Enabled") or not regeneration ("Disabled") during processor pauses.

SDRAM Idle Limit

This option sets the number of "empty" wait cycles before recharging SDRAM modules. The optimal setting improves read/write cycle performance by adjusting the amount of time the memory bank can remain "empty" before recharging, i.e. before rewriting the memory contents back into the cells. However, this installation cannot function as a delay in the regeneration cycle.
Reducing the number of clock cycles from 8 (default) to 0 means that the SDRAM memory bank will be immediately regenerated as soon as the memory controller issues a valid request. When increasing the "SDRAM Idle Limit" from 8 cycles or more, the bank recharge will be delayed by longer time, thereby increasing the time of “storing” information from memory in internal circuits. A read/write command received at this time will be executed instantly. Then we have to admit that memory efficiency will increase when the bank remains “empty” for a longer time. But there is always a BUT! The internal recharging circuits do not store all the rows of the memory bank, but only the row being regenerated. Therefore, an incoming request, for example, to read a certain line, will certainly not “hit the mark”, and the system will have to wait for the regeneration to complete, especially if the parameter value is too high.
Basically, you have to choose between values between 0 and 8 clock cycles, however, as far as the BIOS version allows. Of course, such a setting requires serious experimental verification. Therefore, if it is possible to control the regeneration frequency, then it is better to block this option. Experienced specialists can be recommended to “play” with two characteristics.
The option may be called "DRAM Idle Timer". These options offered two ranges of values:
"Disabled", "0 Cycle", "8 Cycles", "12 Cycles", "16 Cycles", "24 Cycles", "32 Cycles", "48 Cycles",
"0 clocks", "2 clocks", "4 clocks", "8 clocks", "10 clocks", "12 clocks", "16 clocks", "32 clocks".
Such options are quite rare. But the system on a fairly modern AMD751 chipset offered two at once:
"Idle Precharge Limit" with a row of "0 cycles", "8 cycles", "12 cycles", "16 cycles", "24 cycles", "32 cycles", "48 cycles" and "No idle precharge" and "Extra" High Idle Limit" with the values "Disabled"/"Enabled". The last option allows or disables the insertion of an additional wait clock.

SDRAM Precharge Control

- (SDRAM pre-charge control). This option determines whether SDRAM “precharge” is controlled by the central processor or the SDRAM itself. In some BIOS versions, this option may be called (interpreted) as "SDRAM Page Closing Policy" ("method of closing SDRAM pages" - see more in the next section). If this option is disabled ("Disabled"), then all processor cycles to SDRAM are completed with the "All Banks Precharge Command" in the SDRAM memory interface, which improves stability but reduces memory performance. If this option is "Enabled", then the preliminary charge is controlled by the memory chips themselves. This reduces the number of SDRAM precharges and significantly increases the number of CPU-to-SDRAM cycles before memory regeneration is required. This definitely improves overall system performance, but may affect system stability.

SDRAM Refresh

Option to select a regeneration method for SDRAM memory. Possible options: "Serial" (sequential search of rows during regeneration) and "Simultaneous" (simultaneous regeneration). When considering the "Burst Refresh" option, the disadvantages of batch regeneration, in which requests for regeneration are collected into a single package, have already been noted. Rows are "recharged" instantly, but until the full regeneration is complete, access to the memory bus will not be possible. Therefore about optimal installation For specific system it will be possible to speak after experimental tests.
This option was noticed in systems built on SIS620, SIS600 and some others chipsets.

Self-Refresh

Option to enable the "self-regeneration" mode of main memory (if set to "Enabled"). This mode is described in detail above in the introductory article.
The option may also be called "EDO/FPM DRAM Self-Refresh".

Slow Refresh (1:4)

- (slow regeneration). When this option is enabled (“Enabled”), the regeneration circuit will regenerate memory 4 times less often (64 μs versus 16) than in normal mode. This setup improves system performance by reducing contention between the CPU and the regeneration circuit, but not all types of DRAM can support such cycles (in which case a parity error or system crash will be reported). Then you need to set the value to "Disabled". The option at one time became widespread with the development of such a type of PC as the “laptop” (travel PC), as an energy-saving function. In modern systems this option is becoming less and less common.
At one time it was also believed that the use of “slow regeneration” would be quite effective when using 16-bit ISA expansion cards operating in “bus master” mode. Since the ISA card itself can initiate a regeneration request, it is clear that a “slow regeneration” would be less disruptive to data transfer over DMA channels.
The option may also be called "DRAM Slow Refresh", "Slow Refresh" or "Slow Refresh Enable".
The option may also be called "Slow Memory Refresh Divider". But this option set a divisor for slow regeneration: 1, 4, 16 or even 64. Set the largest values, i.e. Only special memory made it possible to reduce the regeneration frequency to the maximum extent.

Staggered Refresh

A hard-to-translate type of regeneration, something like "rolling regeneration". But this incomprehensible term refers to “chessboard” regeneration. As you know, regeneration is performed on memory banks sequentially, with sequential search of rows. But if there are several memory banks and this option is enabled, the memory banks are regenerated simultaneously, but with a shift in line search.
This type of regeneration allows you to smooth out surges in consumption by memory modules, leveling out the currents during various switching processes. Since current surges are reduced, such regeneration is effective in terms of reducing interference.
With this somewhat outdated option, it is possible to set the time interval between regenerated lines, measured in system clock cycles (0T, 1T, 2T, 3T, 4T, 5T, 6T, 7T). Setting it to "0" allows all rows in banks to be regenerated at the same time. But the option can also offer the usual set of values: “allow application”/“deny” (“Enabled” and “Disabled”).
The option may also be called "Refresh Stagger" or "DRAM Refresh Stagger By".