Examples of design for large fpga projects. About documenting projects for PLS
Imagine that the processor, instead of executing a specific set of instructions, will be rebuilt for each program and turn the algorithm directly into hardware. This is exactly how FPGs work. In today's article, I will tell you how this is even possible and introduce you to various FPGA design methods.
To begin with, you need to understand a little about the digital logic of ASIC chips, but starting with them is very difficult and expensive, and it is better to start with FPGAs instead.
What is FPGA?
FPGA stands for field-programmable gate array (user-programmable gate arrays, FPGA). More generally, they are called FPGAs - programmable logic integrated circuits.
Using an FPGA, you can literally design digital microcircuits while sitting at home with an available debug board on the table and developer software for several thousand green rubles. But there are also free options. Please note: it is to design, not to program, because at the output we will get a physical digital circuit that performs a certain algorithm at the hardware level, and not a program for the processor.
It works as follows. There is a ready-made printed circuit board with a set of interfaces that are connected to an FPGA chip installed on the board, something like this cool board for a data center or this debug board for training.
Until we configure the FPGA, there is simply no logic inside the chip to process data from the interfaces, and therefore, of course, nothing will work. But as a result of the design, firmware will be created, which, after loading into the FPGA, will create the digital circuit we need. In this way, you can create a 100G Ethernet controller that will receive and process network packets.
An important feature of FPGA is its reconfigurability. Let's say now we need a 100G Ethernet controller, and in a week the same board can be used to implement four independent 25G Ethernet interfaces.
There are two leading manufacturers of FPGA chips on the market: the well-known Intel and Xilinx. They control 58 and 42% of the market. The founders of Xilinx invented their first FPGA chip back in 1985. Intel entered the market quite recently - in 2015, having absorbed Altera, which was founded at the same time as Xilinx. The Altera and Xilinx technologies are similar in many ways, as are the development environments. I worked more often with Xilinx products, so don’t be surprised by its constant mention in the article.
FPGAs are widely used in various fields: consumer electronics, telecom equipment, accelerator boards for use in data centers, robotics, prototyping ASIC chips. I'll look at a couple of examples below.
We will also look at the technology that provides hardware reconfiguration, get acquainted with the design process, and look at a simple example of implementing a hardware counter in Verilog. If you have any FPGA development board, you should be able to replicate this yourself. If there is no board, you can still get acquainted with Verilog by simulating the operation of the circuit on your computer.
Working principle of FPGA
An FPGA chip is the same custom ASIC chip, consisting of the same transistors from which flip-flops, registers, multiplexers and other logic elements for conventional circuits are assembled. Of course, it is impossible to change the order in which these transistors are connected. But architecturally, the microcircuit is built in such a clever way that it is possible to change the switching of signals between larger blocks: they are called CLBs - programmable logic blocks.
It is also possible to change the logical function that the CLB performs. This is achieved due to the fact that the entire chip is permeated with Static RAM configuration memory cells. Each bit of this memory either controls some kind of signal switching key, or is part of the truth table of a logical function that the CLB implements.
Since the configuration memory is built using Static RAM technology, firstly, when the FPGA is turned on, the chip must be configured, and secondly, the chip can be reconfigured an almost infinite number of times.
Very simplified 2D chip structure without configuration memoryCLBs are located in a switch fabric that defines the connections between the inputs and outputs of the CLBs.
Switching matrix diagramAt each intersection of conductors there are six switching switches controlled by their own configuration memory cells. By opening some and closing others, you can provide different signal switching between CLBs.
CLBCLB very simply consists of a block that defines a Boolean function from several arguments (it is called a Look Up Table, LUT) and a trigger (flip-flop, FF). In modern FPGAs, the LUT has six inputs, but the figure shows three for simplicity. The output of the LUT is fed to the CLB output either asynchronously (directly) or synchronously (via an FF flip-flop running at the system clock).
LUT implementation principleIt is interesting to look at the principle of LUT implementation. Let us have some Boolean function y = (a & b) | ~ c . Its circuit diagram and truth table are shown in the figure. The function has three arguments, so it takes 2^3 = 8 values. Each of them corresponds to its own combination of input signals. These values are calculated by the FPGA firmware development program and written to special configuration memory cells.
The value of each cell is fed to its input of the output multiplexer LUT, and the input arguments of the Boolean function are used to select one or another value of the function. The CLB is the most important hardware resource of the FPGA. The number of CLBs in modern FPGA chips can vary and depends on the type and capacity of the chip. Xilinx has dies with CLB counts ranging from about four thousand to three million.
In addition to the CLB, there are a number of other important hardware resources inside the FPGA. For example, hardware multiply-accumulate units or DSP units. Each of them can perform multiplication and addition operations on 18-bit numbers every clock cycle. In top-end crystals, the number of DSP blocks can exceed 6000.
Another resource is internal memory blocks (Block RAM, BRAM). Each block can store 2 KB. The total capacity of such memory, depending on the crystal, can reach from 20 KB to 20 MB. Like CLBs, BRAMs and DSP blocks are connected by a switch fabric and extend throughout the die. By interconnecting CLB, DSP and BRAM blocks, very efficient data processing circuits can be obtained.
Advantages of FPGA
The first FPGA chip created by Xilinx in 1985 contained only 64 CLBs. At that time, the integration of transistors on chips was much lower than it is now, and digital devices often used "scattered logic" chips. There were separate microcircuits for registers, counters, multiplexers, and multipliers. A specific printed circuit board was created for a specific device, on which these low-integration microcircuits were installed.
The use of FPGA made it possible to abandon this approach. Even an FPGA with a 64 CLB significantly saves space on the printed circuit board, and the availability of reconfiguration has added the ability to update the functionality of devices after manufacturing during operation, as they say “in the field” (hence the name - field-programmable gate array).
Due to the fact that any hardware digital circuit can be created inside an FPGA (the main thing is that there are enough resources), one of the important applications of FPGAs is prototyping ASIC chips.
ASIC development is very complex and expensive, the cost of error is very high, and the issue of logic testing is critical. Therefore, one of the development stages, even before starting work on the physical topology of the circuit, was its prototyping on one or more FPGA chips.
For ASIC development, special boards are produced containing many FPGAs connected to each other. The prototype microcircuit operates at significantly lower frequencies (maybe tens of megahertz), but allows saving on identifying problems and bugs.
However, in my opinion, there are more interesting applications of FPGAs. The flexible structure of the FPGA allows the implementation of hardware circuits for high-speed and parallel data processing with the ability to change the algorithm.
Comparison of hardware platforms Let's think about how CPU, GPU, FPGA and ASIC fundamentally differ. The CPU is universal, you can run any algorithm on it, it is the most flexible, and it is the easiest to use thanks to the huge number of programming languages and development environments.
At the same time, due to the versatility and sequential execution of CPU instructions, the performance decreases and the power consumption of the circuit increases. This happens because for every useful arithmetic operation, the CPU performs many additional operations related to reading instructions, moving data between registers and cache, and other movements.
On the other side is the ASIC. On this platform, the required algorithm is implemented in hardware by directly connecting transistors; all operations are related only to the execution of the algorithm and there is no way to change it. Hence the maximum performance and lowest power consumption of the platform. But it is impossible to reprogram ASIC.
To the right of the CPU is the GPU. These chips were originally designed for graphics processing, but are now also used for general purpose computing mining. They consist of thousands of small computing cores and perform parallel operations on an array of data.
If the algorithm can be parallelized, then the GPU can achieve significant acceleration compared to the CPU. On the other hand, sequential algorithms will be implemented worse, so the platform turns out to be less flexible than the CPU. Also, to develop for GPU you need to have special skills, know OpenCL or CUDA.
Finally, FPGA. This platform combines the efficiency of ASICs with the ability to change the program. FPGAs are not universal, but there is a class of algorithms and tasks that will show better performance on them than on a CPU or even a GPU. The complexity of developing for FPGAs is higher, but new development tools are making this gap smaller.
The decisive advantage of FPGAs is the ability to process data as it arrives with minimal response delay. As an example, you can imagine a smart network router with a large number of ports: when an Ethernet packet arrives on one of its ports, many rules must be checked before selecting an output port. You may need to change some fields in the package or add new ones.
Using an FPGA allows you to solve this problem instantly: the bytes of the packet have just begun to arrive on the chip from the network interface, and its header is already being analyzed. The use of processors here can significantly slow down the speed of processing network traffic. It's clear that routers can have a custom ASIC that performs the most efficiently, but what if the rules for processing packets have to change? Only FPGAs can achieve the required flexibility combined with high performance.
Thus, FPGAs are used where high data processing performance, shortest response time, and low power consumption are needed.
FPGA in the cloud
In cloud computing, FPGAs are used for fast calculations, acceleration of network traffic and access to data arrays. This also includes the use of FPGAs for high-frequency trading on exchanges. FPGA boards with PCI Express and optical network interface manufactured by Intel (Altera) or Xilinx are inserted into the servers.
FPGAs are great for cryptographic algorithms, DNA sequence comparison, and scientific tasks like molecular dynamics. Microsoft has long used FPGAs to accelerate the Bing search service, as well as to organize Software Defined Networking within the Azure cloud.
The machine learning boom has also not spared FPGAs. Xilinx and Intel offer FPGA-based tools for working with deep neural networks. They allow you to obtain FPGA firmware that implements a particular network directly from frameworks like Caffe and TensorFlow.
Moreover, you can try all this without leaving your home and using cloud services. For example, from Amazon you can rent a virtual machine with access to an FPGA board and any development tools, including machine learning.
FPGA on the edge
What else interesting things do FPGAs do? Why don’t they do anything! Robotics, self-driving cars, drones, scientific instruments, medical equipment, consumer mobile devices, smart CCTV cameras and so on.
Traditionally, FPGAs were used for digital processing of one-dimensional signals (and competed with DSP processors) in radar devices, radio transceivers. With increasing chip integration and performance, FPGA platforms have become increasingly used for high-performance computing, such as 2D signal processing at the edge of the cloud.
This concept is most easily understood using a traffic camera with license plate recognition as an example. You can take a camera with the ability to transmit video over Ethernet and process the stream on a remote server. As the number of cameras increases, the load on the network will also increase, which can lead to system failures.
Instead, it is better to implement license plate recognition on a computer installed directly in the video camera body and transmit license plate numbers to the cloud in text format. To do this, you can even take relatively inexpensive FPGAs with low power consumption to make do with a battery. At the same time, it remains possible to change the operating logic of the FPGA, for example, when changing the license plate standard.
As for robotics and drones, in this area it is especially important to fulfill two conditions - high performance and low energy consumption. The FPGA platform is ideal and can be used, in particular, to create flight controllers for drones. They are already making UAVs that can make decisions on the fly.
Project development on FPGA
There are different levels of design: low, block and high. Low level involves using languages like Verilog or VHDL, in which you control development at the register transfer level (RTL). In this case, you form registers, as in a processor, and define logical functions that change the data between them.
FPGA circuits always operate at specific clock speeds (typically 100-300 MHz), and at the RTL level you define the circuit's behavior down to the system clock frequency. This painstaking work results in designs that are as efficient as possible in terms of performance, FPGA die resource consumption, and power consumption. But this requires serious skills in circuit design, and even with them the process is slow.
At the block level, you are mainly engaged in connecting ready-made large blocks that perform certain functions to obtain the system-on-chip functionality you need.
At a high level of design, you no longer control the data at every clock cycle, but instead focus on the algorithm. There are compilers or translators from C and C++ to the RTL level, for example Vivado HLS. It is quite smart and allows you to translate a wide class of algorithms to the hardware level.
The main advantage of this approach over RTL languages is the acceleration of development and especially testing of the algorithm: C++ code can be run and verified on a computer, and this will be much faster than testing algorithm changes at the RTL level. Of course, you have to pay for convenience - the scheme may not be as fast and will take up more hardware resources.
Often we are willing to pay this price: if we use the translator correctly, then the efficiency will not suffer much, and modern FPGAs have enough resources. In our world with a critical time to market indicator, this turns out to be justified.
Often you need to combine all three development styles in one design. Let's say we need to make a device that we could build into a robot and give it the ability to recognize objects in a video stream - for example, road signs. Let's take the video sensor chip and connect it directly to the FPGA. For debugging we can use an HDMI monitor, also connected to the FPGA.
Frames from the camera will be transmitted to the FPGA via an interface that is clearly defined by the sensor manufacturer (USB is not useful here), processed and displayed on the monitor. To process frames, you will need a framebuffer, which is usually located in external DDR memory installed on a printed circuit board next to the FPGA chip.
Typical block diagram of an FPGA design If the video sensor manufacturer does not provide Interface IP for our FPGA chip, then we will have to write it ourselves in RTL, counting clock cycles, bits and bytes in accordance with the data transfer protocol specification. We will most likely take ready-made blocks Preprocess, DDR Controller and HDMI IP and simply connect their interfaces. And we can write the HLS block, which searches and processes incoming data, in C++ and broadcast it using Vivado HLS.
Most likely, we will still need some kind of ready-made library of a detector and classifier of road signs, adapted for use in an FPGA. In this example, of course, I present a highly simplified design flowchart, but it reflects the logic of operation correctly.
Let's look at the design path from writing RTL code to getting a configuration file to load into the FPGA.
Design PathSo you write RTL code that implements the circuit you want. Before testing it on real hardware, you need to make sure that it is correct and correctly solves the required problem. To do this, RTL modeling is used in a simulator on a computer.
You take your circuit, presented only in RTL code for now, and place it on a virtual bench, where you apply sequences of digital signals to the inputs of the circuit, record the output diagrams, the time dependences of the output signals, and compare them with the expected results. Usually you find errors and go back to writing RTL.
Next, the logically verified code is fed as input to the synthesizer program. It converts a textual description of the circuit into a linked list of digital elements from the library available for a given FPGA die. This list will display items such as LUTs, triggers, and the connections between them. At this stage, elements are not yet tied to specific hardware resources. To do this, you need to impose Constraints on the circuit - in particular, specify which physical I/O pins of the FPGA chip the logical inputs and outputs of your circuit are connected to.
These constraints also require that you specify at what clock speeds the circuit must operate. The synthesizer output and constraint file are sent to the Implementation processor, which, among other things, handles Place and Route.
The Place process binds each still anonymous element from the netlist to a specific element inside the FPGA chip. Next, the Route process begins its work, which tries to find the optimal connection of these elements for the corresponding configuration of the FPGA switching matrix.
Place and Route operate based on the constraints we have placed on the circuit: I/O pins and clock speed. The clock period has a very strong influence on Implementation: it should not be less than the time delay on the logic gates in the critical circuit between two successive flip-flops.
Often it is not possible to immediately satisfy this requirement, and then you need to go back to the initial stage and change the RTL code: for example, try to reduce the logic in the critical chain. Once Implementation has completed successfully, we know which elements go where and how they are connected.
Only after this the process of creating a binary FPGA firmware file starts. All that remains is to load it into real hardware and check whether it works as expected. If problems arise at this stage, it means that the modeling was incomplete and all errors and shortcomings were not eliminated at this stage.
You can return to the simulation stage and simulate an emergency situation, and if this does not work, as a last resort, a debugging mechanism is provided directly in the working hardware. You can specify which signals you want to track over time, and the design environment will generate additional logic analyzer circuitry that sits on the chip next to your design, connects to the signals you're interested in, and stores their values over time. The saved timing diagrams of the desired signals can be downloaded to a computer and analyzed.
The article makes an attempt to determine the composition of the accompanying documentation for the developed digital modules for programmable logic integrated circuits (FPGAs). Developers must provide this accompanying documentation to the consumer/customer for the successful further use of the developed digital module in their projects at the stage of designing digital devices on the FPGA.
Introduction
So, what kind of design documentation should the developer be asked if the customer company or enterprise or another developer will subsequently use a “foreign” developed device in their projects? This article can serve as a “cheat sheet” in order to first correctly issue technical specifications for the development of a digital device for FPGAs, and then ask the developer for design documentation for an already developed digital device. Based on previous experience working with design documentation, an enterprise or firm usually uses the following standards and regulatory documents:
- GOST 2.102-68 ESKD. Types and completeness of design documents.
- GOST 15.101-98. System for developing and putting products into production. The procedure for carrying out research work.
- GOST R 15.201-20-00. System for developing and putting products into production. Products for industrial and technical purposes. The procedure for developing and putting products into production.
As a rule, these were firmware files and a program (description of a digital device in VHDL/Verilog or a set of digital circuits developed in a circuit editor using library elements of digital logic, such as flip-flops, registers, counters, decoders, etc.) on CD or DVD and programming instructions. That's all.
The author, for example, faced the following problem. One of the employees developed a complex multi-module digital device. I described all the modules in VHDL, and looked at the cyclograms of the operation of these modules and the digital device as a whole on a good and expensive oscilloscope. He did not know about Test Bench files and the possibility of conducting simulations or did not know how to write them; by the way, there were also no comments on the project and on the module descriptions. The situation can be even worse if the modules are represented by digital circuits designed in a circuit editor using library elements. Here lies one of the main drawbacks: besides the developer himself, it is unlikely that anyone else will understand this digital device, especially if the project is multi-module, and the description of each module is more than 100 lines or more than one monitor screen. This means that if another developer wants to introduce such an already developed digital device for FPGA into a new development or project, he again needs to spend time developing this digital device.
History of the design issue for FPGAs
Currently, the FPGA market is one of the most dynamically developing. FPGAs are used in many industries. At the moment, there is no unambiguous methodology that satisfies all hardware developers for obtaining the FPGA configuration based on the functional model of the device at the system level. The most popular approach to solving this problem is the use of IP core technology (Intellectual Property Cores). IP cores are ready-made components that make it easy to incorporate them into your own project to create a more complex system. This approach has one significant drawback - the attachment of IP nuclei to the elemental basis. Each IP core is optimized for a specific series of chips from a specific manufacturer, which significantly impairs the ability to transfer already created devices from one element base to another. The closed nature of commercial CAD architectures makes it impossible to add your own functional device models at the system level to derive device models at the register transfer level (RTL) based on them. The development of a digital module is carried out in the form of a digital circuit drawn in a circuit editor using the manufacturer’s built-in CAD library of basic circuit elements, such as flip-flops, decoders, counters, adders, etc.
Another popular approach that allows the transition from a functional model at the system level to a device model at the register transfer level is the use of system-level design languages (SLDLs). Such languages include SystemC, Handel-C, VHDL, Verilog, System Verilog. The main advantage is the independence from the hardware base in which the device will be implemented.
Thus, on the one hand, when using IP core technology, the hardware developer receives a high-quality solution, but strictly tied to the hardware basis in which the device is implemented. On the other hand, when using hardware description languages at the system level, the device implementation is hardware independent. From the above it follows that currently it is important to jointly use the hardware description language and IP cores of the manufacturer (Xilinx, Altera, Actel, etc.) and third-party development companies to speed up the design process of digital modules. When using digital modules from third-party manufacturers, sometimes there is a lack of information in the accompanying documentation.
Providing information about the developed digital module for FPGA
Depending on the methodology for obtaining the FPGA configuration based on the functional model of the device at the system level, the developer can distinguish the following types of digital module for the FPGA:
- Software - a developed digital module, transmitted to the consumer in the form of a description in the hardware description language (VHDL, Verilog) and/or developed in the Schematic Editor for further use in programs for automated synthesis of logic circuits and optimized for functional parameters.
- Firmware - a digital module developed by a third-party development company, called an IP core, transmitted to the consumer in the form of a logical circuit (netlist) based on the FPGA manufacturer’s logical element library and optimized for functional and electrical parameters.
At the stage of documentation development, based on personal experience, it is necessary to draw up, in addition to the usual design documentation and specifications carried out in accordance with GOST 15.101, GOST 15.201, GOST 2.102, GOST 2.114, documentation for all types of models (system, logical, circuit engineering) created at the stages of designing digital devices on FPGAs.
In other words, the set of design documentation for a digital device for FPGAs, in addition to the firmware file, programming instructions and a recorded project on CD/DVD, must also include accompanying documentation.
Table. List of sections of accompanying documentation
| Section title | View | |
| Software | Firmware | |
| General information | ||
| Purpose and scope | ABOUT | R |
| Specifications | ABOUT | ABOUT |
| Description of reset signals | ABOUT | ABOUT |
| Description of synchronization signals | ABOUT | ABOUT |
| Description of interfaces | ABOUT | R |
| Timing diagrams | R | ABOUT |
| Description of control registers | ABOUT | ABOUT |
| Structural (functional) diagram | R | R |
| Programming Guide | ABOUT | ABOUT |
| FPGA model or family, company manufacturer |
R | ABOUT |
| Digital Module Presentation for logic design on FPGA |
||
| RTL model | ABOUT | No |
| Logic model | No | ABOUT |
| Design Constraints | ABOUT | ABOUT |
Here is a list of sections (table) that should be included in the accompanying documentation for a digital module project for FPGAs. For each section, signs of the need to include the section in the set of documents are shown:
- “O” is a required section;
- “P” is the section recommended for delivery.
Recommended file formats for submitting supporting documentation are MS Word, PDF (best format), HTML. Description files in the hardware description language (VHDL, Verilog) and/or developed in the Schematic Editor are provided in the form required by the CAD software for development. An exception may be the additional provision in graphic format (JPEG, BMP) of digital circuit files developed in the Schematic Editor.
General information
This section describes the general information about the developed digital module in the form of a description:
- functional diagram and its component blocks/parts;
- reset signals, synchronization;
- applied interfaces;
- control registers;
- time diagram;
- programming.
Purpose and scope
The purpose of the digital module and its areas of application are determined.
Specifications
A description of its main technical characteristics is provided, such as performance, power consumption for a specific FPGA chip, the number of occupied gates, and the type of FPGA chip used. Additionally, the FPGA manufacturer's CAD software used in the development of the digital module and the software used for modeling and verification are indicated. For all programs used, the version and installed updates are indicated. A graphical representation of the digital module in the form of a “black box” is provided with the designation of external inputs/outputs and a brief description of their purpose is given.
Description of reset signals
Details of reset signals are given below:
- List of external and internal reset signals.
- Timing parameters and timing diagrams of reset signals.
- Circuits for generating internal reset signals, if any, are part of the digital module.
- Relationships with other signals (especially synchronization signals).
Description of synchronization signals
Here are the details about the synchronization signals:
- description of external synchronization signals;
- timing parameters of synchronization signals;
- description of internal synchronization signals and the scheme for their generation;
- timing relationships between synchronization signals from different sources;
Description of interfaces
Features of the use of all interfaces that are part of the developed digital module are given, preferably unified for organizing interaction with other nodes of the system on a chip. Additionally, an Internet link to a complete description of the standard interface is provided, or a description of the interface itself is provided. At the moment, AMBA, PLB, and Wishbone bus interfaces are accepted as unified interfaces for digital modules.
Timing diagrams
The necessary information is provided for organizing data exchange through interfaces and other inputs/outputs of the digital module: graphical representation of timing diagrams, description of data transfer protocols, requirements for external signals supplied to the digital module (duration, frequency, etc.), and other information .
Description of control registers
A description of all control registers of the digital module is provided. A typical control register description contains the register name, the register address in the internal address space, the initial value after the reset signal is removed, the access type (read/write), and a description of the internal fields.
Structural (functional) diagram
An image of the internal structure of the connections of the main internal nodes/blocks of the digital module is provided, as well as their brief text description. Additionally, a description of the main internal blocks of the digital module is given. The purpose of this document is to provide the consumer with the information necessary to understand the principles of operation of the digital module.
The number of blocks described and the scope of the description are determined by the developer of the digital module. It is preferable that the minimum number of modules described correspond to the number of elements of the structural (functional) diagram of the digital module.
A typical description of the indoor unit contains:
- purpose of the block;
- structural (functional) diagram of the block (if necessary);
- operating modes and algorithms;
- work time diagrams;
- organization of block management;
- organization of communication with other blocks;
- any other information.
Programming Guide
Provides all the necessary information about the programming process using the CAD software of the manufacturer of the digital module in the FPGA, the required tools for software development and debugging, and software libraries.
FPGA model or family, manufacturer
For Firmware of a digital module, the FPGA manufacturer, model or family of FPGA and its speed characteristics are indicated. For the Software digital module, information is provided on the amount of resources occupied and the requirements for the used FPGA.
Representation of a digital module for logic design
The article discussed the difficulties in using a “foreign” project in VHDL - the lack of suitable guidelines for naming and rules for writing programs. Also given were general guidelines on names, good manners for writing programs, and guidelines for synthesis. These issues should be discussed in as much detail as possible with the developer if in the future you plan to continue development or upgrading on your own, before he starts developing the RTL model of the digital module on the FPGA. This especially applies to the type of Software digital module on FPGA. This part of the article describes the general requirements for the entire project of the developed digital module on FPGA. Here are the issues that you should pay attention to when drawing up technical specifications for the development of a digital module on an FPGA, and this especially concerns the transfer of work results.
RTL model
A digital module, described in a synthesized subset of the Verilog or VHDL language and/or developed in the Schematic Editor, is intended for use at the stage of FPGA logic synthesis. Delivered to Software in the form of an assembled digital module project in the CAD software of the FPGA manufacturer. For the digital Firmware module, the RTL model is provided under a separate agreement.
In addition to the RTL model files, the following are transmitted:
- Instructions for using the model.
- Description of the memory blocks included in the model, including memory type, size, number of memory blocks, hierarchical name of the memory block.
- Description of the process of creating ready-made kernels using programs to create them (for example, CoreGenerator for Xilinx ISE). In the absence of descriptions, there may be limitations for re-design and application due to technology and manufacturer dependence.
- In the case of using a microprocessor from a manufacturer (for example, from Altera - Nios processor; from Xilinx - Microblaze, PowerPC microprocessors), a description of the process of configuring the processor core and its peripherals is required.
- A set of tests (Test Bench files) for verification and simulation of a digital module, written in Verilog and/or VHDL and/or System Verilog.
- Any other additional information.
Logic model
The model is a list of circuits described using Verilog or VHDL languages in the basis of the FPGA manufacturer's library, and is supplied for the Firmware of the digital module.
In addition to the logical model files, the following are transmitted:
- Instructions for using this model.
- A set of tests (Test Bench files) for verification and simulation of a digital module, written in Verilog and/or VHDL and/or System Verilog.
- Guide to working with a set of tests for modeling and verification of a digital module.
- Any other additional information.
Design Constraints
Design constraints are provided as a file describing a set of constraints imposed on the digital module when it is included in the system-on-chip logic model. This set includes clock constraints, timing constraints, restrictions on the interaction of the digital module with other modules, and operating conditions for the digital module. The Synopsis Design Constraints (SDC) format or the FPGA manufacturer's CAD format is preferred.
A sample list of restrictions for synchronization signals:
- time diagram (Clock waveform);
- clock frequency instability (Jitter);
- changing the clock frequency phase;
- duration of switching times (Transition times);
- timing diagrams of derived clock waveforms;
- any other additional information.
A set of restrictions for synchronization signals is required for Software and Firmware digital modules.
Sample list of time restrictions:
- Arrival times at inputs;
- time of appearance of signals at outputs (Required times at outputs);
- Multi-cycle paths;
- false paths;
- duration of data signal switching times (Data signal transition times);
- any other additional information.
Conclusion
The following set of accompanying documentation for the developed digital modules for FPGAs is provided by agreement between the consumer and the developer. Most often, the developer simply provides a digital module described in VHDL, Verilog, System Verilog and/or developed in a circuit editor. Regarding additional documentation, the developer’s answer is most often the following: “The digital module works, so take it and use it. There is nothing complicated in describing the circuit in hardware language: you can figure it out yourself.”
In the author’s opinion, you can figure out anything, it all depends on the desire and time spent, and the time spent on understanding “someone else’s” project for an already developed digital module is directly proportional to the experience of describing equipment in VHDL, Verilog and knowledge digital and microprocessor circuitry. This can be avoided if you initially agree with the developer on the composition of the accompanying documentation, then the use of the digital module in your project becomes easier, and its implementation will happen faster.
To summarize, the author would like to note that when formulating the task of developing a digital device on an FPGA, one should adhere to the recommendations given in the article, then problems will not arise when reusing or upgrading a previously developed digital device.
Literature
- Denisov A. Some tips for designing digital devices on VHDL for FPGAs // Components and Technologies. 2009. No. 12.
- GOST 2.102-68 ESKD. Types and completeness of design documents.
- GOST 2.114-95 ESKD. Technical conditions.
- GOST 15.101-98. System for developing and putting products into production. The procedure for carrying out scientific research work.
- GOST R 15.201-20-00. System for developing and putting products into production. Products for industrial and technical purposes. The procedure for developing and putting products into production.
Introduction
The VHDL language is the de facto international standard in digital system design automation, and is the input language of many modern computer-aided design (CAD) systems for both custom and field programmable logic integrated circuits (FPGAs) and field programmable gate arrays. VHDL is intended, first of all, for specification - an accurate description of the systems being designed and their modeling at the initial stages of design - algorithmic and logical. Using VHDL, you can simulate electronic circuits taking into account real time delays.
Recently, systems for synthesizing circuits based on specifications in this language have been very successfully developed. For example, using the Xilinx Foundation Series 2.1i CAD system, you can simulate the original circuit description in VHDL, and then synthesize the circuit and obtain a setup (configuration) file for a Xilinx FPGA chip. The use of CAD MAX+PLUSII allows you to solve similar problems for programmable microcircuits manufactured by Altera.
VHDL is a powerful language, it allows you to describe behavior, i.e. algorithms for the functioning of digital systems, as well as carry out a hierarchical functional-structural description of systems, has tools for describing parallel asynchronous processes, regular (systolic) structures and at the same time has all the features of a high-level programming language - it allows you to create your own data types, has a wide range arithmetic and logical operations, etc.
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Laboratory work No. 1
FPGA EXPRESS DEBUGGER
1. General job description
1.1. The goal of the work is to gain skills to work with the FPGA EXPRESS debugger.
Laboratory work consists of homework and laboratory assignments. Your homework is to independently master the most basic features of the debugger and familiarize yourself with its purpose. The laboratory task involves entering your version of an example program written in VHDL, and using its example to master the principles of working with the FPGA EXPRESS debugger.
Using the methodological manual, familiarize yourself with the purpose and capabilities of the debugger of digital device models in the VHDL language.
3. Theoretical part
FPGA Express translates and optimizes VHDL descriptions into an internal format equivalent to the primitive gate level. This format is then compiled into FPGA technology.
To work with VHDL, you need to be familiar with the following concepts:
Hardware description languages.
Using FPGA Express.
Model of the design process.
The US Department of Defense developed in 1982 VHSIC HDL(VHDL) as part of the Very High Speed IC (VHSIC) program. VHDL describes the behavior, functions, inputs, and outputs of a digital circuit. VHDL is similar in style and syntax to modern programming languages, however, it includes many specific hardware constructs. FPGA Express reads and parses supported VHDL syntax.
Hardware description languages
Hardware Description Languages (HDL) are used to describe the architecture and behavior of discrete electronic systems. These languages are designed for building complex projects. Historical analogies are often made about how software description languages can be called, from machine codes (transistors and soldering) to assembly languages (network lists) to high-level languages (HDL).
HDL-based systems are useful when developing large projects where several developers or even several teams work together. HDLs provide structured programming. Once the basic architectural decisions have been made and the main components and connections between them have been identified, work on the subprojects can proceed completely independently.
Typical HDL Applications
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Advantages of HDL
The design methodology using HDL has several fundamental advantages over traditional component-level design methodology. Among these advantages, the following should be noted:
You can check the functionality of the project very early and simulate it immediately. Modeling a project at such a high level before translation into elementary execution allows you to test many architectural and design solutions.
FPGA Express provides logic synthesis and optimization so that it is possible to automatically transform a VHDL description into an elementary-level execution for the selected technology. This methodology eliminates component-level bottlenecks and reduces design time and errors introduced by manually translating a VHDL program into specific elements. By using logical optimization FPGA Express can automatically convert a synthesized design into the smallest and fastest circuit. In addition, it is possible to assign information obtained from circuit synthesis and optimization back to the existing VHDL description, which leads to more precise tuning of architectural solutions.
HDL descriptions provide technology-independent documentation of a design and its functionality. These programs are much easier to read and understand than netlists or diagrams. Due to the fact that the initial HDL description of the project is technology independent, it can be used to generate projects with different technologies without affecting the original one.
VHDL, like most high-level languages, produces rigid type checking. Components whose type is declared as a four-bit signal cannot be connected to a three- or five-bit signal; such a mismatch will result in a compilation error. If the range of variables is defined from 1 to 15, then an error will occur when assigning the value 0 to them. Incorrect use of types is the main source of errors when composing descriptions. Type checking detects such errors even before the project is generated.
Debugging in FPGA Express
To debug you need to do the following:
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2. Connect the created file to the project in FPGA Express.
To connect a file to a project, you need to create the project itself:
Select menu File / New.
Enter the project name.
When requesting project files, you must find the file(s) created in step 1 with a ready-made description of the device (component).
When the project file(s) are correctly connected, a window appears divided into two parts: Design Sources and Chips (Fig. 1). Where Design Sources is a window for working with project files, Chips is a window for working with synthesized devices.
Fig.1. Project Window
To make it easier to work with the project file(s), the Design Sources window displays the name(s), location(s) of the file(s), as well as the presence of syntax and lexical errors or inaccuracies.
When you hover the cursor and simultaneously click the right mouse button on any of the names in this window, the following context menu appears (Fig. 2):
Update Project - analysis of the project for inaccuracies or errors.
Force Update Project - a complete analysis of all project files for errors or inaccuracies.
Create Implementation - creating a device model.
Edit File - editing a file.
Identify Sources - connecting the file to the project.
New library - connecting your own library to the project.
Project Report - project report (short description in the form of an external text file).
Remove - removes a file or library from the project.
As in all applications with a user-friendly interface, each context menu item is duplicated by a simple menu and buttons on the panel.
Fig.3. Part of the file with an error
Editing a file is similar to text editors, the only difference being that deleting characters or lines can only be done using the Back Space key.
After the correction, to search for other existing errors in this window, you need to right-click and select Analyze File (search for inaccuracies or errors) in the active context menu. Further after successful editing, it is advisable to save the current changes.
If there are no errors, then the corresponding file will have its synthesized version (i.e., the device model described in the internal FPGA Express format, as shown in Fig. 4).
Fig.4. Sign of a synthesized variant of the CODER device
The synthesized version is an intermediate link for the successful creation of a digital device model.
4. Work progress
4.1 Using any text editor, type a description of the digital device in accordance with your option. To prevent errors, the file must have a *.vhd extension.
4.2 Create a project in the FPGA Express debugger and connect the typed file to it.
4.3 After correctly connecting the description file, create a report on your project using FPGA Express.
Name;
Goal of the work;
Equipment used;
Theoretical part;
Description of the sequence of actions when debugging your version;
Printout of the project report;
1. What is the FPGA Express application and what are its main functions?
2. What, in your opinion, are the advantages and disadvantages of HDL as a hardware description language?
3. What is the sequence of actions when debugging the VHDL description of your device?
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Laboratory work No. 2
KEY FEATURES OF THE FPGA EXPRESS DEBUGER
1. General job description
1.1. The purpose of the work is to study the possibilities of synthesis and optimization of the FPGA EXPRESS debugger.
Laboratory work consists of homework and laboratory assignments. Homework is to review the principles of debugging VHDL descriptions. The lab assignment involves entering your version of an example program written in VHDL and learning the principles of synthesis and optimization of the designed device using the FPGA EXPRESS debugger.
1.3. Equipment used
To perform laboratory work, a personal computer such as an IBM PC, a color monitor with a VGA or higher graphics adapter, and a printer are used.
2. Homework and guidelines for completing it
According to the methodological manual, familiarize yourself with and repeat the purposes and capabilities of the debugger of digital device models in the VHDL language.
3. Theoretical part
Design methodology
In Fig. Figure 5 shows a typical design procedure that uses FPGA Express and a VHDL simulator. Each step of this design model is described in detail.
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Rice. 5. Block diagram of design stages
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2. Providing VHDL language test drivers for the simulator. Drivers provide test vectors for simulation and collect output data.
3. Modeling the project using the VHDL simulator. Checking the correctness of the project description.
4. Using FPGA Express to synthesize and optimize the VHDL design description into an elementary netlist. FPGA Express generates optimized netlists that satisfy the timing constraints of the selected FPGA architecture.
5. Using the FPGA design system (Design Manager) to communicate a specific FPGA technology version with the VHDL simulator. The design system includes the simulation models and interfaces needed for end-to-end design.
6. Simulation of a specific technological version of the project using a VHDL simulator. It is possible to use the original VHDL simulation drivers from point 2, since the module and port definitions are preserved during the translation and optimization process.
7. Compare the output of the element-level simulation (item 6) with the output of the original VHDL description (item 3) to verify that the execution is correct.
Project Hierarchy
FPGA Express supports hierarchical boundaries defined using VHDL structural constructs. These boundaries lead to two main results:
1. Each design object defined in the VHDL description is synthesized separately and maintained as an independent project. This respects design constraints and allows each object to be optimized separately in FPGA Express.
2. Component implementations within VHDL definitions are maintained during input. The implementation name that is assigned to each user object persists until it is executed at the element level.
Note. FPGA Express does not support or automatically create a hierarchy of other non-structural VHDL constructs such as blocks, processes, loops, functions, and procedures. These VHDL description elements are translated in the context of their projects. After reading the VHDL design, you can group process logic, functions, or procedures together inside the FPGA Express Implementation Window.
The choice of hierarchical boundaries has a significant impact on the quality of the synthesized project. With FPGA Express, you can optimize your design while maintaining its hierarchical boundaries. FPGA Express only partially optimizes logic across hierarchical modules. Full optimization is possible in those parts of the design hierarchy that are compressed in FPGA Express.
An example of the hierarchical structure of a complex device is shown in Fig. 6
Rice. 6. Hierarchical structure
Data types
In VHDL, you must assign a type to all ports, signals, and variables. The data type of an object is determined by the operation that can be assigned to it. For example, the AND operator is defined for objects of type BIT but not for objects of type INTEGER. Data types are also important when synthesizing a project. The data type of an object determines its size (bit width) and bit organization. Choosing the right data types significantly improves the quality of the project and helps minimize the number of errors.
Design Constraints
It is necessary to describe the qualitative limitations of the design module inside the FPGA Express Implementation Window.
Register selection
The placement of registers and clock circuits is a very important architectural decision. There are two ways to define registers in your VHDL definition. Each of these methods has certain advantages:
1. Implement registers directly in the VHDL description, selecting any desired element from the FPGA library. Clock circuits can be of arbitrary complexity. An architecture based on flip-flops or latches is selected. The main disadvantages of this approach are:
The VHDL description is now technology specific because you have selected building blocks from the technology library. However, it is possible to isolate this section of the project as a separate object, which is then linked to the rest of the project.
The program is written more difficult.
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Asynchronous projects
It is possible to use FPGA Express to design asynchronous designs with multiple and controlled clock pulses. However, although these designs are logically (statistically) correct, they may not model or operate correctly due to race conditions.
Language constructs
Another component of the VHDL synthesis policy is a set of constructs that describe a design, they define its architecture, and they produce consistently good results. Registers are implemented using component constructs.
Laboratory work No. 3
VHDL MODELS SIMULATOR MODELSIM
1. General job description
1.1. The purpose of the work is to get acquainted with the VHDL model simulator ModelSim.
Laboratory work consists of homework and laboratory assignments. Homework is to review the principles of debugging, synthesizing, and optimizing VHDL descriptions using the FPGA Express debugger. The lab assignment involves entering a version of an example program written in VHDL and simulating and analyzing your device using the ModelSim simulator.
1.3. Equipment used
To perform laboratory work, a personal computer such as an IBM PC, a color monitor with a VGA or higher graphics adapter, and a printer are used.
2. Homework and guidelines for completing it
According to the methodological manual, familiarize yourself with and repeat the assignments and all the main features of the debugger of digital device models in the VHDL language.
3. Theoretical part
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Rice. 10. Scheme of an active digital device
Here, in addition to describing the structure and function of the element itself, it is necessary to create an additional device that generates a certain sequence of logical input states (possibly the input part of the truth table) of the Schaeffer element.
Simulations in ModelSim
If there are no errors at the stages of connecting the file with the original active device for simulation, you can begin the simulation process itself.
Depending on the purposes of the simulation, the ModelSim system provides: a console for the time sampling of the simulation, as well as the ability to directly monitor almost all key processes occurring on the device (the latter will be discussed in the next laboratory work).
Let's look at modeling controls. In this sense, for full control over the modeling process you need: the main menu Run and Options. In the Run menu, all items are intended for control, and in the Options menu, there is the Simulate Options item (setting private modeling parameters).
When you activate the Simulate Options item, a panel for entering simulation parameters appears (Figure 14).
This panel contains three tabs:
VSIM- directly modeling parameters. The following parameters are set here:
Default Run length - setting the minimum time sampling of the modeling process.
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Suppress Warnings - disable/enable the system's response to warnings associated with various types of inaccuracies.
Default Force Kind - setting the ability to control the modeling process (Freeze (no control) / Drive (control) / Deposit (fully under control)).
Default Radix - default signal type (Symbolic (symbolic) / binary (binary) / octal (octal) / decimal (decimal) / hex (hexadecimal)).
Figure 14 - Simulate Options panel
Ase Protective actions of the system against various types of errors (Fig. 15):
rtion- Break On simulation. (Note (comment) /warning (error)).
Ignore Assertions for - setting limits for ignoring the protection system. (Note (comment) / warning (inaccuracy) / error (- setting the parameters for outputting the source file in the Source window error) / failure ("failure")).
system actions
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4. Work progress
5. Directions
Theoretical part;
Description of the sequence of actions when setting a device description for modeling;
Conclusions on the work done.
5.2. Test questions for laboratory work
1. What is the need to use modeling systems like ModelSim.
2. What are the shortcomings of the system, if any?
3. In your opinion, what is the scope of application of the ModelSim system?
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Laboratory work No. 4
SIMULATOR MODELSIM
1. General job description
1.1. The goal of the work is to gain skills for modeling designed devices in the ModelSim system.
Laboratory work consists of homework and laboratory assignments. The homework is to review the principles of working with the ModelSim simulator, mastered in the previous laboratory work. The laboratory task consists of connecting your version of an example program written in VHDL and conducting a full simulation and analysis of the designed device using ModelSim.
1.3. Equipment used
To perform laboratory work, a personal computer such as an IBM PC, a color monitor with a VGA or higher graphics adapter, and a printer are used.
2. Homework and guidelines for completing it
Review material learned in previous lessons.
3. Theoretical part
and output) / Internal Signals (internal signals)).
For this purpose, a system of information and functional information windows (Main menu View) was created in ModelSim. The main condition for the operation of all windows is a correctly connected source file with a VHDL description of the simulated device.
Let's look at the principles of working with it:
1.Source- window with the contents of the source VHDL file (Fig. 16). Allows you to set breakpoints (this requires double-clicking the left mouse button on the line number). To change the contents of the window, you need to activate the Select Source File... item of the main File menu (you can change the source file only to a file connected to the project), or double-click the left mouse button in the window for report design and Test questions
5.1. The laboratory report must contain:
Name;
Goal of the work;
equipment used;Structure on the name of the required file. Note: the window does not allow editing source files.
Fig. 16. Source Window
2. Structure - a window containing the structure and subordination of project files (Fig. 17). Provides a helper function for the Source window.
Rice. 17. Structure Window
3. Variables
- the window contains all the internal variable constructs of the VHDL language used to describe the current connected model (Fig. 18). Has only an informational function.
4. Signals – a window containing a list and values of all input/output ports and signals (Fig. 19). The window records any changes to the contents of all I/O ports and signals. It is possible to delete, add or install a limited number of signals or ports in this window, depending
Value- current signal value.Rice. 21. Force Signal Window
Delay- delay time of the current signal value (the scale of the value is indicated to the right of the input field).
Second Value value - the next state of this signal or I/O port.
: To enter exactly the type of delay before changing the current value, the recommended value is that Note warning errors associated with device simulation, re Delay for second value- the value is provided for the device being designed.
its state for the next one (Second Value). Note: the value of this field must be equal to both signal delays.
Repeat Every - This field is an optional parameter for modeling, because implies a period of repetition of changes in the state of an I/O port or signal value. A field is included in the main change parameters when the checkbox next to it is activated.
Note: the value of this field must necessarily be greater than the value in the Delay for second Value field, since the initial time reference point of the modeling process is common for all signal delays.
Kind- setting the degree of autonomy of the changes made. (Freeze (the system autonomously manages changes) / Drive (possibility of control) / Deposit (uncontrolled control by the designer)).
To confirm the entered parameters for signal changes or I/O port, click the Apply button.
To set parameters for changes to another signal, you must first select it in the Signals window.
It is possible to set a limited list of signals using the Signal window, where you can select the most necessary ones, and the Add to List item (sub-item Selected Signals (adds a selected group to the List window)). In addition, all signals of the current project (using the Signals in Design sub-item), all active signals at the moment of modeling (using the Signals in Region sub-item) or signals participating in any information flow (using the Dataflow window) can be added to the list (selecting the required flow) and the sub-item Signals from DataFlow...).Note.
The minimum step for recording changes in signal values is set in the parameters of the simulation process (Options.../ Simulate Options...). The window provides various options related to recording signal changes and saving the resulting table in a separate file.
6. Process – a window containing the name and state of VHDL processes of the current simulated device (Fig. 23). It is possible to display limited processes when using the Processes item in the main Options menu (it is possible to display all active processes (View Active Processes) or active processes at the current modeling step (iteration).
Rice. 23. Process Window
7. Wave – the window required to display the timing diagrams of a specific set of signals or input/output ports (Fig. 24).
Rice. 24. Wave Window
The window has all the properties of a flexible means of monitoring signal changes within the time frame of the modeling process itself. In conjunction with the Signals window and the Add to Waveform item of the Signals main menu, this window has the ability to define a limited list of signals, the Selected Signals subitem (installation of signals selected in the Signals window into the work list), the Signals in Region subitem (monitoring active signals at the current simulation iteration ), sub-item Signals in Design (installation of all project signals), sub-item Signals from DataFlow (installation of signals participating in the selected information flow from the DataFlow window)). Like all functional windows, this window has the ability to work with the list of output signals (Cursor and Edit window menus), and allows you to control the output of time diagrams (Zoom and Options window menus). An additional auxiliary tool is a slider (installed at any point on the diagram using the mouse), which fixes the simulation time in the current position. In addition, when changing the position of the slider, if the values of any of the signals change in the next position, the corresponding changes are recorded in the list of displayed signals (to the left of the diagrams, as shown in Fig. 24).
8. DataFlow – a window displaying the organization of all information flows present in the simulated device (Fig. 25).
Rice. 25. DataFlow Window
Like most functional windows, this window works in conjunction with other windows:
Signals (this window allows you to select the signal(s) in question for further visualization of the information flows associated with it (them) in the DataFlow window).
Process (using this window you can select a process to further demonstrate its information flows).
4. Work progress
4.1. Using any text editor, type a description of the digital device in accordance with your option. To prevent errors, the file must have a *.vhd extension.
4.2. Create a project in the ModelSim modeling system and connect to it the file typed and debugged in FPGA Express.
4.3. After correctly connecting the description file, install the system to test your device.
4.4. Conduct testing and full analysis of your digital device according to your option.
5. Instructions for preparing the report and Test questions
5.1. The laboratory report must contain:
Name;
Goal of the work;
Equipment used;
Theoretical part;
Description of the sequence of actions during the process of analysis and modeling of your option;
Printout of all states, all signals;
A printout of your source file;
Printout of timing diagrams and processes;
Conclusions on the work done.
5.2. Test questions for laboratory work
1. What are the main functions of the Signals and Wave windows?
2. How important is visualization of the structure of information flows in a device during design?
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Laboratory work No. 5
INTRODUCING VHDL LANGUAGE
1. General job description
IMPLEMENTATION OF THE PROJECT ON FPGA
After testing the logic circuit using functional modeling, it is necessary to place it on the chip. Then simulate the circuit taking into account the actual element delays obtained after placing the circuit on the chip. If necessary, adjust the resulting solutions. After which the circuit is loaded into the FPGA and tested on the bench.
Rice. 82. Stages of designing a digital device on FPGA
Main stages of design on FPGA (from lectures):
A device diagram is developed and entered into XILINX.
IMPLEMENTATION is performed (translation, circuit formation by extracting library elements, optimization, placement on the chip).
Programming.
Associative memory. Organization, sampling method, differences from address storage.
Associative access implements the search for information based on some characteristic, and not on its location in memory (address or place in the queue). In the most complete version, all words stored in memory are simultaneously checked for compliance with a feature, for example, for the coincidence of certain word fields (tags - from the English word tag) with the feature specified by the input word (tag address). Words that satisfy the criterion are output. The discipline for issuing words if several words satisfy a tag, as well as the discipline for writing new data, may be different. The main area of application of associative memory in modern computers is data caching.
In associative storage devices, information is searched according to an associative feature recorded in each memory cell.
A word is written to the mask register that allows a query for all or only some bits of the associative attribute; using a mask allows you to shorten or expand the search area.
The search for information is carried out in parallel across all cells by comparing the request with the associative feature of each cell.
The search result is generated by a special combinational circuit that generates signals notifying about the absence of words that satisfy the search conditions, about the presence of only one word, about the presence of several words that have such an associative feature.
After generating and processing the warning signals, the control circuit reads the necessary information. When writing, a free cell is found based on the occupancy bit value, and information is written to the first free cell found.
The occupancy digit is checked by setting the nth digit (busy digit) of the mask. When using additional combinational circuits in associative memory, you can perform various logical operations, determining the maximum or minimum number, the number of words that have the same associative feature, etc. The memory cells of an associative storage device must be elements of static memory; in associative memory, all cells are accessed simultaneously and must not be interrupted by regeneration cycles. Associative memory is the fastest, but very expensive, since it requires the introduction of an additional comparison circuit that allows searching for each memory cell. Therefore, such memory is usually not used in its pure form, and high-speed cache-type memory devices are usually implemented as partially associative.
INfully associative cache memory (FACM, Fully Associated Cache Memory), each cell stores data, and in the “tag” field - the full physical address of the information, a copy of which is recorded. During any exchanges, the physical address of the requested information is compared with the “tag” fields of all cells and if they match, the Hit signal is set in any cell.
When reading and the signal value Hit = 1, the data is output to the data bus, but if there are no matches (Hit = 0), then when reading from the main memory, the data along with the address are placed in a free or most recently unused cache memory cell.
When writing, data along with the address are first, as a rule, placed in cache memory (in a detected cell with Hit = 1 and free with Hit = 0). Copying data to main memory is performed under the control of a special controller when there are no memory accesses.
FACM memory is a very complex device and is used only in small capacities, mainly in special applications. At the same time, this type of cache memory provides the greatest functional flexibility and absence of address conflicts, since any unit of information can be loaded into any cache memory cell.
From the lectures:
Associative storage devices
The fundamental difference is that the system for retrieving information from them is carried out not according to a unique address where the information is located, but according to a certain characteristic, which is, in fact, part of the information being sought.
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Information |
A tag is a distinctive feature, by coincidence with which a piece of information is obtained.
Simplified diagram of an associative memory:
Storage zone is an addressable memory with numbered cells that stores information and tags.
To access associative memory, a sample of the desired tag is placed in the request register. The comparison scheme compares the query. A match is established on the match register where the tag from memory matched the sample. Reactions are possible (no matches; there is at least one match - in this case, the found cell is placed in the data register; multiple matches - the CS must decide which cell to get for processing).
Application: database, knowledge base, PC as a cache.
65 nanometers is the next goal of the Zelenograd plant Angstrem-T, which will cost 300-350 million euros. The company has already submitted an application for a preferential loan for the modernization of production technologies to Vnesheconombank (VEB), Vedomosti reported this week with reference to the chairman of the board of directors of the plant, Leonid Reiman. Now Angstrem-T is preparing to launch a production line for microcircuits with a 90nm topology. Payments on the previous VEB loan, for which it was purchased, will begin in mid-2017.
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Rostec is “fencing itself” and encroaching on the laurels of Samsung and General Electric
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