Components within a PC interact with each other in various ways. Majority internal components, including the processor, cache, memory, expansion cards and storage devices communicate with each other using one or more tires(buses).

A bus in computers is a channel through which information is transferred between two or more devices (usually a bus that connects only two devices is called port- port). A bus typically has access points, or places that a device can connect to to make itself part of the bus, and devices on the bus can send information to and receive information from other devices. The concept of a bus is quite general both for the “inside” of the PC and for the outside world. For example, a telephone connection in a house can be thought of as a bus: information travels along wires in the house, and one can connect to the "bus" by installing a telephone jack, plugging a telephone into it, and picking up the telephone. All phones on the bus can share information, i.e. speech.

This material is dedicated to the tires of modern PCs. First, tires and their characteristics are discussed, and then the most common tires in the world are discussed in detail. I/O buses(Input/Output bus), also called expansion buses(expansion buses).

Tire functions and characteristics

PC buses are the main data "paths" on the motherboard. The main one is system bus(system bus), which connects the processor and main memory RAM. Previously, this bus was called local, but in modern PCs it is called front tire(Front Side Bus - FSB). Characteristics system bus determined by the processor; The modern system bus is 64 bits wide and operates at 66, 100 or 133 MHz. Such high frequency signals create electrical noise and other problems. Therefore, the frequency must be reduced so that the data reaches expansion cards(expansion card), or adapters(adapters), and other more remote components.

However, the first PCs had only one bus, which was shared by the processor, RAM memory, and I/O components. Processors of the first and second generations operated at a low clock frequency and all system components could support this frequency. In particular, this architecture made it possible to expand RAM capacity using expansion cards.

In 1987, Compaq developers decided to separate the system bus from the I/O bus so that they could work with at different speeds. Since then, this multi-bus architecture has become the industry standard. Moreover, modern PCs have several I/O buses.

Tire hierarchy

The PC has a hierarchical organization of various buses. Most modern PCs have at least four buses. The bus hierarchy is explained by the fact that each bus is increasingly moving away from the processor; each bus connects to the level above it, combining various components RS. Each bus is usually slower than the bus above it (for the obvious reason - the processor is the fastest device in the PC):

• Internal cache bus: This is the fastest bus that connects the processor and the internal L1 cache.
• System bus: This is the second level system bus that connects the memory subsystem to the chipset and processor. On some systems, the processor and memory buses are the same thing. This bus operated at a speed (clocking frequency) of 66 MHz until 1998, and then it was increased to 100 MHz and even 133 MHz. Pentium II and higher processors implement an architecture with double independent bus(Dual Independent Bus - DIB) - the single system bus is replaced by two independent buses. One of them is intended for accessing main memory and is called front tire(frontside bus), and the second one is for accessing the L2 cache and is called rear tire(backside bus). The presence of two buses increases the performance of the PC, since the processor can simultaneously receive data from both buses. In fifth-generation motherboards and chipsets, the L2 cache is connected to the standard memory bus. Note that the system bus is also called main bus(main bus), processor bus(processor bus), memory bus(memory bus) and even local bus(local bus).
• Local I/O bus: This high-speed I/O bus is used to connect fast peripheral devices to the memory, chipset, and processor. This bus is used by video cards, disk drives and network interfaces. The most common local I/O buses are the VESA Local Bus (VLB) and the Peripheral Component Interconnect (PCI) bus.
• Standard I/O bus: The “deserved” standard I/O bus is connected to the three buses considered, which is used for slow peripheral devices (mouse, modem, sound cards, etc.), as well as for compatibility with older devices. In almost all modern PCs, such a bus is the ISA (Industry Standard Architecture) bus.
• Universal Serial Bus(Universal Serial Bus - USB), allowing you to connect up to 127 slow peripheral devices using hub(hub) or daisy-chaining devices.
• High-speed serial bus IEEE 1394 (FireWire), designed for connecting digital cameras, printers, TVs and other devices that require extremely high bandwidth to a PC.

Multiple I/O buses connecting various peripherals to the processor are connected to the system bus using bridge(bridge), implemented in the chipset. The system chipset manages all buses and ensures that every device in the system communicates correctly with every other device.

New PCs have an additional "bus" that is specifically designed for graphical interaction only. In fact, this is not a tire, but port- Accelerated Graphics Port (AGP). The difference between a bus and a port is that a bus is usually designed to share media between multiple devices, while a port is designed to only share two devices.

As shown earlier, I/O buses are actually an extension of the system bus. On the motherboard, the system bus ends at the chipset chip, which forms a bridge to the I/O bus. Buses play a vital role in data exchange in a PC. In fact, all PC components, with the exception of the processor, communicate with each other and the system RAM through various I/O buses, as shown in the figure on the left.

Address and data buses

Each tire consists of two different parts: data bus(data bus) and address bus(address bus). When most people talk about a bus, they think of a data bus; The data itself is transmitted along the lines of this bus. The address bus is a set of lines whose signals determine where to send or receive data.

Of course, there are signal lines to control the operation of the bus and signal the availability of data. Sometimes these lines are called control bus(control bus), although they are often not mentioned.

Tire width

A bus is a channel through which information “flows.” The wider the bus, the more information can "flow" along the channel. The first ISA bus on the IBM PC was 8 bits wide; the general purpose ISA bus currently in use is 16 bits wide. Other I/O buses, including VLB and PCI, are 32 bits wide. System bus width in PC s Pentium processors is 64 bits.

The width of the address bus can be determined independently of the width of the data bus. The address bus width indicates how many memory cells can be addressed during data transfer. In modern PCs, the address bus width is 36 bits, which allows addressing memory with a capacity of 64 GB.

Bus speed

Bus speed(bus speed) shows how many bits of information can be transmitted on each bus conductor per second. Most buses carry one bit per clock cycle on a single wire, although newer buses such as AGP can carry two bits of data per clock cycle, doubling the performance. The old ISA bus requires two clock cycles to transfer one bit, cutting performance in half.

Bus bandwidth

Width (bits) Speed ​​(MHz) Bandwidth (MB/s) 8-bit ISA 16-bit ISA 64-bit PCI 2.1 AGP (x2 mode) AGP (x4 mode)

Bandwidth(bandwidth) also called throughput(throughput) and shows the total amount of data that can be transferred over the bus in a given unit of time. The table shows theoretical bandwidth of modern I/O buses. In fact, the tires do not reach the theoretical value due to overhead for executing commands and other factors. Most tires can operate at different speeds; The following table shows the most typical values.

Let's make a note about the last four lines. Theoretically, the PCI bus can be expanded to 64 bits and 66 MHz speed. However, for compatibility reasons, almost all PCI buses and devices on the bus are only rated at 33 MHz and 32 bits. AGP builds on the theoretical standard and operates at 66 MHz, but retains a 32-bit width. AGP has additional modes x2 and x4, which allow the port to perform data transfers two or four times per clock cycle, increasing the effective bus speed to 133 or 266 MHz.

Bus interface

In a multi-bus system, the chipset must provide circuitry to combine the buses and communicate between a device on one bus and a device on another bus. Such schemes are called bridge(bridge) (note that a bridge is also a network device for connecting two different types of networks). The most common is the PCI-ISA bridge, which is a component of the system chipset for PCs with Pentium processors. The PCI bus also has a bridge to the system bus.

Bus mastering

In high-capacity buses, a huge amount of information is transmitted over the channel every second. Typically a processor is required to control these transfers. In effect, the processor acts as a "middleman" and, as is often the case in the real world, it is much more efficient to remove the middleman and perform the transfers directly. For this purpose, devices have been developed that can control the bus and act independently, i.e. transfer data directly to system RAM memory; such devices are called driving tires(bus masters). Theoretically, the processor can perform other work simultaneously with data transfers on the bus; In practice, the situation is complicated by several factors. For correct implementation bus mastering(bus mastering) arbitration of bus requests is required, which is provided by the chipset. Bus mastering is also called "first party" DMA, since the operation is controlled by the device performing the transfer.

Currently, bus mastering is implemented on the PCI bus; Support has also been added for IDE/ATA hard drives to implement bus mastering on PCI under certain conditions.

Local bus principle

The beginning of the 90s is characterized by the transition from text-based applications to graphical ones and the growing popularity of operating Windows systems. This has led to a huge increase in the amount of information that must be transferred between the processor, memory, video and hard drives. A standard monochromatic (black and white) text screen contains only 4000 bytes of information (2000 for character codes and 2000 for screen attributes), while a standard 256-color Windows screen requires more than 300,000 bytes! Moreover, modern resolution of 1600x1200 with 16 million colors requires 5.8 million bytes of information per screen!

The transition of the software world from text to graphics also meant increased program sizes and increased memory requirements. From an I/O perspective, processing the additional data for a video card and huge capacity hard drives requires much more I/O bandwidth. This situation had to be faced with the advent of the 80486 processor, the performance of which was much higher than previous processors. The ISA bus no longer met the increased requirements and became a bottleneck in increasing PC performance. Increasing the speed of a processor does little if it must wait on a slow system bus to transfer data.

The solution was found in the development of a new, faster bus, which was supposed to complement the ISA bus and be used specifically for such high-speed devices as video cards. This bus had to be placed on (or near) the much faster memory bus and run at approximately the external speed of the processor in order to transfer data much faster than the standard ISA bus. When such devices were placed near ("locally") the processor, local bus. The first local bus was the VESA Local Bus (VLB), and the modern local bus in most PCs is the Peripheral Component Interconnect (PCI) bus.

System bus

System bus(system bus) connects the processor to the main RAM memory and, possibly, to the L2 cache. It is the central bus of the computer and the other buses “branch” from it. The system bus is implemented as a set of conductors on the motherboard and must correspond to a specific type of processor. It is the processor that determines the characteristics of the system bus. At the same time, the faster the system bus, the faster the remaining electronic components of the PC must be.

Old CPUs Tire width Bus speed 8088 8 bits 4.77 MHz 8086 16 bits 8 MHz 80286-12 16 bits 12 MHz 80386SX-16 16 bits 16 MHz 80386DX-25 32 bits 25 MHz

Let's consider system buses of a PC with processors of several generations. In processors of the first, second and third generations, the system bus frequency was determined by the operating frequency of the processor. As processor speed increased, so did the system bus speed. At the same time, the address space increased: in the 8088/8086 processors it was 1 MB (20-bit address), in the 80286 processor the address space was increased to 16 MB (24-bit address), and starting with the 80386 processor the address space was 4 GB (32 -bit address).

Family 80486 Tire width Bus speed 80486SX-25 32 bits 25 MHz 80486DX-33 32 bits 33 MHz 80486DX2-50 32 bits 25 MHz 80486DX-50 32 bits 50 MHz 80486DX2-66 32 bits 33 MHz 80486DX4-100 32 bits 40 MHz 5X86-133 32 bits 33 MHz

As can be seen from the table for fourth generation processors, the system bus speed initially corresponded to operating frequency processor. However, technological advances made it possible to increase the processor frequency, and matching the system bus speed required increasing the speed of external components, mainly system memory, which was associated with significant difficulties and cost restrictions. Therefore, the 80486DX2-50 processor was used for the first time frequency doubling(clock doubling): the processor worked with internal clock frequency 50 MHz, and external The system bus speed was 25 MHz, i.e. only half the operating frequency of the processor. This technique significantly improves computer performance, especially due to the presence of an internal L1 cache, which satisfies most of the processor's access to system memory. Since then frequency multiplication(clock multiplying) has become in a standard way improves computer performance and is used in all modern processors, and the frequency multiplier is increased to 8, 10 or more.

Pentium family Tire width Bus speed Intel P60 64 bits 60 MHz Intel P100 64 bits 66 MHz Cyrix 6X86 P133+ 64 bits 55 MHz AMD K5-133 64 bits 66 MHz Intel P150 64 bits 60 MHz Intel P166 64 bits 66 MHz Cyrix 6X86 P166+ 64 bits 66 MHz Pentium Pro 200 64 bits 66 MHz Cyrix 6X86 P200+ 64 bits 75 MHz Pentium II 64 bits 66 MHz

For a long time, PC system buses with fifth-generation processors operated at speeds of 60 MHz and 66 MHz. A significant step forward was the increase in data width to 64 bits and the expansion of the address space to 64 GB (36-bit address).

The system bus speed was increased to 100 MHz in 1998 thanks to the development of production of PC100 SDRAM chips. RDRAM memory chips can further increase the speed of the system bus. However, the transition from 66 MHz to 100 MHz had a significant impact on processors and motherboards with Socket 7. In Pentium II modules, up to 70-80% of traffic (information transfers) is carried out inside the new SEC (Single Edge Cartridge), which houses the processor and both caches are L1 cache and L2 cache. This cartridge operates at its own speed, independent of the system bus speed.

CPU Chipset Speed tires CPU speed Intel Pentium II 82440BX 82440GX 100 MHz 350,400,450 MHz AMD K6-2 Via MVP3, Aladdin V 100 MHz 250,300,400 MHz Intel Pentium II Xeon 82450NX 100 MHz 450.500 MHz Intel Pentium III i815 i820 133 MHz 600.667+ MHz AMD Athlon VIA KT133 200 MHz 600 - 1000 MHz

The i820 and i815 chipsets, designed for the Pentium III processor, are designed for a 133 MHz system bus. Finally, the AMD Athlon processor introduced significant changes to the architecture and the concept of a system bus turned out to be unnecessary. This processor can run various types of RAM at a maximum frequency of 200 MHz.

Types of I/O buses

This section will cover various I/O buses, with much of it dedicated to modern buses. A general idea of ​​the use of I/O buses is given by the following figure, which clearly shows the purpose of the various I/O buses of a modern PC.

The following table summarizes the various I/O buses used in modern PCs:

Tire	Year	Width	Speed	Max. checkpoint ability
PC and XT	1980-82	8 bits	Synchronous: 4.77-6 MHz	4-6 MB/s
ISA (AT)	1984	16 bits	Synchronous: 8-10 MHz	8 MB/s
M.C.A.	1987	32 bits	Asynchronous: 10.33 MHz	40 MB/s
EISA (for servers)	1988	32 bits	Synchronous: max. 8 MHz	32 MB/s
VLB, for 486	1993	32 bits	Synchronous: 33-50 MHz	100-160 MB/s
PCI	1993	32/64 bit	Asynchronous: 33 MHz	132 MB/s
USB	1996	Sequential		1.2 MB/s
FireWire (IEEE1394)	1999	Sequential		80 MB/s
USB 2.0	2001	Sequential		12-40 MB/s

Old tires

The new modern PCI bus and AGP port were “born” from old buses that can still be found in PCs. Moreover, the oldest ISA bus is still used even in the latest PCs. Next we will look at the old PC tires in a little more detail.

Industry Standard Architecture (ISA) bus

This is the most common and truly standard bus for PCs, which is used even in the latest computers despite the fact that it has remained virtually unchanged since its expansion to 16 bits in 1984. Of course, it is now supplemented by faster buses, but it “survives” thanks to the presence of a huge base of peripheral equipment designed for this standard. In addition, there are many devices for which ISA speed is more than enough, such as modems. According to some experts, it will take at least 5-6 years before the ISA bus “dies”.

The choice of the width and speed of the ISA bus was determined by the processors with which it worked in the first PCs. The original ISA bus on the IBM PC was 8 bits wide, corresponding to the 8 bits of the external data bus of the 8088 processor, and ran at 4.77 MHz, which is also the speed of the 8088 processor. In 1984, the IBM AT computer appeared with an 80286 processor and the bus width was doubled up to 16 bits, like the external data bus of the 80286 processor. At the same time, the bus speed was increased to 8 MHz, which also matched the speed of the processor. Theoretically, the bus throughput is 8 MB/s, but in practice it does not exceed 1-2 MB/s.

In modern PCs, the ISA bus acts as internal bus, which is used for keyboard, floppy disk, serial and parallel ports, and how external expansion bus, to which you can connect 16-bit adapters, such as a sound card.

Subsequently, AT processors became faster, and then their data bus was increased, but now the requirement for compatibility with existing devices forced manufacturers to adhere to the standard and the ISA bus has remained virtually unchanged since then. The ISA bus provides sufficient bandwidth for slow devices and is sure to guarantee compatibility with almost every PC released.

Many expansion cards, even modern ones, are still 8-bit (you can tell by the card's connector - 8-bit cards only use the first part of the ISA connector, while 16-bit cards use both parts). For these cards, the low bandwidth of the ISA bus does not matter. However, access to interrupts IRQ 9 through IRQ 15 is provided through wires in the 16-bit portion of the bus connectors. This is why most modems cannot be connected to IRQs with large numbers. IRQ lines between ISA devices cannot be shared.

Document The PC99 System Design Guide, prepared by Intel and Microsoft, categorically requires the removal of ISA bus slots from motherboards, so we can expect that the days of this “well-deserved” bus are numbered.

MicroChannel Architecture (MCA) bus

This bus was IBM's attempt to make the ISA bus "bigger and better." When the 80386DX processor with a 32-bit data bus was introduced in the mid-1980s, IBM decided to develop a bus to match this data bus width. The MCA bus was 32 bits wide and had several advantages over the ISA bus.

The MCA bus had some great features considering it was introduced in 1987 i.e. seven years before the advent of the PCI bus with similar capabilities. In some respects, the MCA bus was simply ahead of its time:

• Width 32 bits: The bus was 32 bits wide, like the local VESA and PCI buses. Its throughput was much higher compared to the ISA bus.
• Bus mastering: The MCA bus effectively supported bus mastering adapters, including proper bus arbitration.
• The MCA bus automatically configured the adapter cards, making jumpers unnecessary. This happened 8 years before Windows 95 made PnP technology generally accepted on PCs.

The MCA bus had enormous potential. Unfortunately, IBM made two such decisions that did not promote the adoption of this bus. Firstly, the MCA bus was incompatible with the ISA bus, i.e. ISA cards did not work at all in PCs with an MCA bus, and the computer market is very sensitive to the problem of backward compatibility. Secondly, IBM decided to make the MCA bus its own without licensing its use.

These two factors, combined with the higher cost of MCA bus systems, led to the oblivion of the MCA bus. Since PS/2 computers are no longer in production, the MCA bus is "dead" for the PC market, although IBM still uses it in its RISC 6000 UNIX servers. The MCA bus story is one of the classic examples of how in the world of computers non-technical issues often dominate technical issues.

Extended Industry Standard Architecture (EISA) bus

This bus never became as standard as the ISA bus and was not widely used. In fact, it was Compaq's answer to the MCA bus and led to similar results.

Compaq avoided two of IBM's biggest mistakes when developing the EISA bus. Firstly, the EISA bus was compatible with the ISA bus and, secondly, all PC manufacturers were allowed to use it. In general, the EISA bus had significant technical advantages over the ISA bus, but the market did not accept it. Main features of the EISA bus:

• ISA bus compatibility: ISA cards could work in EISA slots.
• Bus width 32 bits: Bus width increased to 32 bits.
• Bus mastering: The EISA bus effectively supported bus mastering adapters, including proper bus arbitration.
• Plug and Play (PnP) technology: The EISA bus automatically configured adapter cards similar to the PnP standard of modern systems.

EISA-based systems are now sometimes found in network file servers, but it is not used in desktop PCs due to higher costs and the lack of a wide selection of adapters. Finally, its throughput is significantly inferior to local buses VESA Local Bus and PCI. In fact, the EISA bus is now close to dying.

VESA Local Bus (VLB)

The first one is quite popular local bus VESA Local Bus (VL-Bus or VLB) appeared in 1992. The abbreviation VESA stands for Video Electronics Standards Association, and this association was created in the late 80s to solve the problems of video systems in PCs. The main reason for the development of the VLB bus was to improve the performance of PC video systems.

The VLB bus is a 32-bit bus that is a direct extension of the 486 processor's memory bus. The VLB bus slot is a 16-bit ISA slot with a third and fourth slot added at the end. The VLB typically operates at 33 MHz, although higher speeds are possible on some systems. Since it is an extension of the ISA bus, an ISA card can be used in a VLB slot, but it makes sense to occupy the normal ISA slots first and leave a small number of VLB slots for VLB cards, which of course do not work in ISA slots. The use of a VLB graphics card and I/O controller significantly improves system performance compared to a system with only a single ISA bus.

Despite the fact that the VLB bus was very popular in PCs with the 486 processor, the advent of the Pentium processor and its local PCI bus in 1994 led to the gradual "oblivion" of the VLB bus. One of the reasons for this was Intel's efforts to promote the PCI bus, but there were also several technical problems associated with the implementation of VLB. First, the bus design is very much tied to the 486 processor, and the move to Pentium caused compatibility issues and other problems. Secondly, the tire itself had technical shortcomings: a small number of cards on the bus (often two or even one), synchronization problems when using multiple cards, and lack of support for bus mastering and Plug and Play technology.

Now the VLB bus is considered obsolete and even the latest motherboards with a 486 processor use the PCI bus, while Pentium processors use only PCI. However, PCs with a VLB bus are inexpensive and can sometimes still be found.

Peripheral Component Interconnect (PCI) bus

The most popular I/O bus right now interactions between peripheral components(Peripheral Component Interconnect - PCI) was developed by Intel in 1993. It was aimed at fifth and sixth generation systems, but was also used in the latest generation of motherboards with the 486 processor.

Like the VESA Local Bus, the PCI bus is 32 bits wide and typically runs at 33 MHz. The main advantage of PCI over the VESA Local Bus lies in the chipset that controls the bus. The PCI bus is controlled by special circuitry in the chipset, and the VLB bus was basically just an extension of the 486 processor bus. The PCI bus is not "tied" to the 486 processor in this regard and is provided by the chipset correct management bus and bus arbitration, allowing PCI to do much more than the VLB could. The PCI bus is also used outside the PC platform, providing versatility and reducing the cost of system development.

In modern PCs, the PCI bus acts as internal bus which connects to the EIDE channel on the motherboard, and how external expansion bus, which has 3-4 expansion slots for PCI adapters.

The PCI bus is connected to the system bus through a special “bridge” and operates at a fixed frequency regardless of the processor clock frequency. It is limited to five expansion slots, but each of them can be replaced with two devices built into the motherboard. The processor can also support multiple bridge chips. The PCI bus is more strictly specified than the VL-Bus and provides several additional capabilities. In particular, it supports cards with a supply voltage of +3.3 V and 5 V, using special keys that prevent the card from being inserted into the wrong slot. Next, the operation of the PCI bus is discussed in more detail.

PCI bus performance

The PCI bus actually has the highest performance among common I/O buses in modern PCs. This is due to several factors:

• Burst mode: The PCI bus can transfer information in burst mode, where after initial addressing, several sets of data can be transferred in a row. This mode is similar to cache bursting.
• Bus mastering: The PCI bus supports full mastering, which improves performance.
• High Bandwidth Options: Version 2.1 of the PCI bus specification allows expansion to 64 bits and 66 MHz, increasing current performance by four times. In practice, the 64-bit PCI bus has not yet been implemented in the PC (although it is already used in some servers) and the speed is currently limited to 33 MHz, mainly due to compatibility issues. For some time you will have to limit yourself to 32 bits and 33 MHz. However, thanks to AGP, higher performance will be realized in a slightly modified form.

Depending on the chipset and motherboard, the PCI bus speed can be set as synchronous or asynchronous. In a synchronous setup (used in most PCs), the PCI bus operates at half the speed of the memory bus; since the memory bus typically runs at 50, 60, or 66 MHz, the PCI bus runs at 25, 30, or 33 MHz. With an asynchronous setup, the PCI bus speed can be set independently of the memory bus speed. This is usually controlled using jumpers on the motherboard or BIOS settings. "Overclocking" of the system bus in a PC that uses a synchronous PCI bus will cause "overclocking" of peripheral PCI devices, often causing system instability problems.

The original implementation of the PCI bus ran at 33 MHz, and the subsequent PCI 2.1 specification specified a frequency of 66 MHz, which corresponds to a throughput of 266 MB/s. The PCI bus can be configured for 32- and 64-bit data widths and allows for 32- and 64-bit cards, as well as interrupt sharing, which is useful in high-performance systems that lack IRQ lines. Since mid-1995, all high-speed PC devices have been communicating with each other via the PCI bus. Most often it is used for hard drive controllers and graphics controllers, which are mounted directly on the motherboard or on expansion cards in PCI bus slots.

PCI bus expansion slots

The PCI bus allows more expansion slots than the VLB bus without causing technical problems. Most PCI systems support 3 or 4 PCI slots, and some support significantly more.

Note: On some systems, not all slots support bus mastering. This is less common now, but it is still recommended to look at the motherboard manual.

The PCI bus allows for a greater variety of expansion cards compared to the VLB bus. The most common types are video cards, SCSI host adapters, and high-speed network cards. (Hard drives also operate on the PCI bus, but they are usually connected directly to the motherboard.) Note, however, that the PCI bus does not implement some functions; for example, serial and parallel ports must remain on the ISA bus. Fortunately, even today the ISA bus remains more than sufficient for these devices.

PCI bus internal interrupts

The PCI bus uses its internal interrupt system to handle requests from cards on the bus. These interrupts are often called "#A", "#B", "#C" and "#D" to avoid confusion with the normally numbered system IRQs, although they are sometimes also called "#1" through "#4". These interrupt levels are usually invisible to the user except in the PCI BIOS setup screen, where they can be used to control the operation of PCI cards.

These interrupts, if required by the cards in the slots, are mapped to regular interrupts, most often to IRQ9 - IRQ12. PCI slots on most systems can be mapped to most of the four common IRQs. On systems that have more than four PCI slots, or that have four slots and a USB controller (which uses PCI), two or more PCI devices share an IRQ.

PCI bus mastering

Recall that bus mastering is the ability of devices on the PCI bus (different, of course, from the system chipset) to take control of the bus and directly perform transfers. The PCI bus was the first bus that led to the popularity of bus mastering (probably because the operating system and programs were able to take advantage of it).

The PCI bus supports full bus mastering and provides a means of bus arbitration through the system chipset. The PCI design allows multiple devices to master the bus at the same time, and the arbitration circuit ensures that no device on the bus (including the processor!) will block any other device. However, one device is allowed to use the full bandwidth of the bus if no other devices are transmitting anything. In other words, the PCI bus acts as a tiny local area network inside the computer, in which multiple devices can communicate with each other by sharing a communication channel, and which is controlled by the chipset.

Plug and Play technology for PCI bus

The PCI bus is part of the Plug and Play (PnP) standard developed by Intel, Microsoft, and many others. PCI bus systems were the first to popularize the use of PnP. PCI chipset circuits manage card identification and work with the operating system and BIOS to automatically allocate resources to compatible cards.

The PCI bus is constantly being improved and development is led by the PCI Special Interest Group, which includes Intel, IBM, Apple, and others. The result of these developments was an increase in the bus frequency to 66 MHz and data expansion to 64 bits. However, alternatives are being created, such as Accelerated Graphics Port (AGP) and FireWire (IEEE 1394) high-speed serial bus. AGP is actually a 66 MHz PCI bus (version 2.1) that introduces some improvements aimed at graphics systems.

Another initiative is the tire PCI-X, also called "Project One" and "Future I/O". IBM, Mylex, 3Com, Adaptec, Hewlett-Packard and Compaq want to develop a special high-speed server version of the PCI bus. This bus will have a bandwidth of 1 GB/s (64 bits, 133 MHz). Intel and Dell Computer are not involved in this project.

Dell Computer, Hitachi, NEC, Siemens, Sun Microsystems and Intel, in response to Project One, took the initiative to develop the Next-Generation I/O bus ( NGIO), targeting a new I/O architecture for servers.

In August 1999, seven leading companies (Compaq, Dell, Hewlett-Packard, IBM, Intel, Microsoft, Sun Microsystems) announced their intention to combine the best ideas of Future I/O and Next Generation I/O buses. The new open I/O architecture for servers should provide throughput of up to 6 GB/s. The new NGIO standard is expected to be adopted by the end of 2001.

Accelerated graphics port

The need to increase the bandwidth between the processor and the video system initially led to the development of a local I/O bus in the PC, starting with the VESA Local Bus and ending with the modern PCI bus. This trend continues, with the demand for increased video bandwidth no longer being met even by the PCI bus with its standard 132 MB/s bandwidth. 3D graphics(3D graphics) allows you to simulate virtual and real worlds on the screen with the smallest details. Displaying textures and hiding objects requires huge amounts of data, and the graphics card must have quick access to this data in order to maintain high refresh rates.

Traffic on the PCI bus becomes very busy in modern PCs when video, hard drives and other peripherals compete for the only I/O bandwidth. To prevent saturation of the PCI bus with video information, Intel developed a new interface specifically for the video system, called accelerated graphics port(Accelerated Graphics Port - AGP).

The AGP port is designed in response to the increasing demand for video performance. As programs and computers use areas such as 3D acceleration and full-motion video playback, the processor and video chipset must process more and more information. In such applications, the PCI bus has reached its limit, especially since it is also used by hard drives and other peripheral devices.

In addition, more and more video memory is required. Three-dimensional graphics require more memory, not only for the screen image, but also for calculations. Traditionally, this problem is solved by placing more and more memory on the video card, but this poses two problems:

• Price: Video memory is more expensive than regular RAM memory.
• Limited Capacity: The memory capacity on a video card is limited: if you put 6 MB on the card and 4 MB is required for the frame buffer, then there is only 2 MB left for processing. This memory is not easy to expand and cannot be used for anything else unless video processing is needed.

AGP solves these problems by allowing the video processor to access main system memory to perform calculations. This technique is much more efficient, since this memory can be dynamically divided between system processor and a video processor depending on the needs of the system.

The idea behind implementing AGP is quite simple: to create a fast, specialized interface between the video chipset and the system processor. The interface is implemented only between these two devices, which provides three main advantages: it is easier to implement the port, it is easier to increase AGP speed, and video-specific enhancements can be introduced into the interface. The AGP chipset acts as an intermediary between the processor, Pentium II L2 cache, system memory, video card and PCI bus, implementing the so-called quad port(Quad Port).

AGP is considered a port, not a bus, since it only connects two devices (the processor and the video card) and does not allow expansion. One of the main advantages of AGP is that it isolates the video system from the rest of the PC components, eliminating competition for bandwidth. Since the graphics card is removed from the PCI bus, other devices can run faster. For AGP, the motherboard has a special socket, which is similar to the PCI bus socket, but is located in a different location on the board. In the following figure, you can see two ISA bus sockets (black), then two PCI bus sockets (white) and an ADP socket (brown).

AGP appeared at the end of 1997 and was the first to be supported by the 440LX Pentium II chipset. The following year, AGP chipsets from other companies appeared. For more information about AGP, see the website http://developer.intel.com/technology/agp/.

AGP interface

The AGP interface is similar to the PCI bus in many respects. The slot itself has the same physical shape and dimensions, but is offset further from the edge of the motherboard than PCI slots. The AGP specification actually relies on the PCI 2.1 specification, which allows 66 MHz speeds, but this speed is not implemented in the PC. AGP motherboards have one expansion slot for an AGP video card and one less PCI slot, but are otherwise similar to PCI motherboards.

Bus width, speed and bandwidth

The AGP bus is 32 bits wide, just like the PCI bus, but instead of running at half the memory bus speed like PCI does, it runs at full speed. For example, on a standard Pentium II motherboard, the AGP bus runs at 66 MHz instead of the 33 MHz PCI bus. This immediately doubles the port's bandwidth - instead of the 132 MB/s limit for PCI, the AGP port has a bandwidth of 264 MB/s in the lowest speed mode. Additionally, it does not share any bandwidth with other PCI bus devices.

In addition to doubling the bus speed, AGP defines a mode 2X, which uses special signals to allow twice as much data to be transmitted through the port at the same clock frequency. In this mode, information is transmitted on the rising and falling edges of the synchronization signal. While the PCI bus only transmits data on one edge, AGP transmits data on both edges. As a result, performance doubles further and theoretically reaches 528 MB/s. It is also planned to implement the regime 4X, in which four transfers are carried out in each clock cycle, which will increase performance to 1056 MB / s.

Of course, all this is impressive and the bandwidth of 1 GB/s is very good for a video card, but there is one problem: a modern PC has several buses. Recall that Pentium-class processors have a 64-bit data bus width and operate at 66 MHz, which provides a theoretical throughput of 524 MB/s, so 1 GB/s bandwidth does not provide a significant gain unless the data bus speed is increased beyond 66 MHz . New motherboards have increased the system bus speed to 100 MHz, which increases throughput to 800 MB/s, but this is not enough to justify mode transfers 4X.

In addition, the processor must access system memory, not just the video system. If the entire system bandwidth of 524 MB/s is occupied by video via AGP, what can the processor do? In this case, moving to a system speed of 100 MHz will provide some benefit.

AGP Port Video Pipelining

One of the benefits of AGP is its ability to pipeline data requests. Pipelining was first used in modern processors as a way to improve performance by overlapping sequential chunks of tasks. Thanks to AGP, the video chipset can use a similar technique when requesting information from memory, which significantly improves performance.

AGP access to system memory

The most important feature of AGP is the ability to share the main system memory with the video chipset. This allows the video system to access more memory for 3D graphics and other processing without requiring large amounts of video memory on the video card. Memory on the video card is shared between the frame buffer and other uses. Because the framebuffer requires fast and expensive memory such as VRAM, most cards all memory is executed in VRAM, although this is required for memory areas other than the framebuffer.

Note that AGP Not refers to the unified memory architecture (UMA). In this architecture all The video card memory, including the frame buffer, is taken from the main system memory. In AGP, the frame buffer remains on the video card, where it is located. The frame buffer is the most important component of video memory and requires the highest performance, so it makes more sense to leave it on the video card and use VRAM for it.

AGP allows the video processor to access system memory for other memory-intensive tasks, such as texturing and other 3D graphics operations. This memory is not as critical as the frame buffer, which allows video cards to be cheaper by reducing VRAM memory capacity. Accessing system memory is called direct execution from memory(DIrect Memory Execute - DIME). A special device called graphic aperture remapping table(Graphics Aperture Remapping Table - GART), operates on RAM addresses in such a way that they can be distributed in system memory in small blocks, rather than one large section, and provides them to the video card as if it were part of video memory. The following figure gives a clear idea of ​​AGP functions:

AGP requirements

To use AGP in a system, several requirements must be met:

• Availability of AGP video card: This requirement is quite obvious.
• Availability of a motherboard with an AGP chipset: Of course, the chipset on the motherboard must support AGP.
• Operating system support: The operating system must support the new interface using its internal drivers and routines.
• Driver support: Of course, the video card requires special drivers to support AGP and use it special abilities, for example mode 3X.

New serial buses

For 20 years now, many peripheral devices have been connected to the same parallel and serial ports that appeared on the first PC, and with the exception of the Plug and Play standard, “I/O technology” has changed little since 1081. However, by the end of the 90s of the last century, users increasingly began to feel the limitations of standard parallel and serial ports:

• Bandwidth: Serial ports have a maximum throughput of 115.2 Kb/s, and parallel ports (depending on type) about 500 Kb/s. However, devices such as digital video cameras require significantly higher bandwidth.
• Ease of use: Connecting devices to old ports is very inconvenient, especially through parallel port adapters. In addition, all ports are located on the back of the PC.
• Hardware resources: Each port requires its own IRQ line. The PC has only 16 IRQ lines, most of which are already occupied. Some PCs have only five free IRQ lines for connecting new devices.
• Limited number of ports: Many PCs have two serial COM ports and one parallel LPT port. It is possible to add more ports but at the cost of using valuable IRQ lines.

In recent years, I/O technology has become one of the most dynamic areas of desktop PC development, and two serial data standards have been developed that have greatly changed the way peripheral devices are connected and have taken the concept of plug and play to new heights. Thanks to the new standards, any user will be able to connect an almost unlimited number of devices to a PC in just a few seconds, without having any special technical knowledge.

Universal Serial Bus

Developed by Compaq, Digital, IBM, Intel, Microsoft, NEC and Northern Telecom universal serial bus(Universal Serial Bus - USB) provides a new connector to connect all common I/O devices, eliminating many of today's ports and connectors.

The USB bus allows connection of up to 127 devices using daisy chain connection(daisy-chaining) or use USB hub(USB hub). The hub itself, or hub, has several sockets and is inserted into a PC or other device. Each USB hub can connect seven peripheral devices. Among them there may be a second hub, to which seven more peripheral devices can be connected, etc. The USB bus also carries +5 V power along with the data signals, so small devices such as hand-held scanners may not have their own power supply.

The devices plug directly into the 4-pin socket on the PC or hub as a Type A rectangular socket. All cables that are permanently connected to the device have a Type A plug. Devices that use a separate cable have a Type B square socket, and the cable that connects them has a Type A or Type B plug.

The USB bus removes the speed limitations of UART-based serial ports. It operates at a speed of 12 Mbps, which is compatible with Ethernet and Token Ring network technologies and provides sufficient bandwidth for all modern peripheral devices. For example, the USB bus has enough bandwidth to support devices such as external CD-ROM drives and tape drives, as well as the ISDN interfaces of feature phones. It is also sufficient for transmitting signals digital audio directly into speakers equipped with digital-to-analog converters, eliminating the need for a sound card. However, the USB bus is not intended to replace networks. To achieve an acceptable low cost, the distance between devices is limited to 5 m. For slow devices such as keyboards and mice, the data transfer rate can be set to 1.5 Mbps, saving bandwidth for faster devices.

The USB bus fully supports Plug and Play technology. It eliminates the need to install expansion cards inside the PC and subsequently reconfigure the system. The bus allows you to connect, configure, use and, if necessary, disconnect peripheral devices while the PC and other devices are working. There is no need to install drivers, select serial and parallel ports, or define IRQ lines, DMA channels, and I/O addresses. All this is achieved by controlling peripheral devices using a host controller on the motherboard or PCI card. The host controller and slave controllers in the hubs control peripheral devices, reducing processor load and improving overall system performance. The host controller itself is controlled by system software within the operating system.

Data is transmitted over a bidirectional channel controlled by the host controller and slave hub controllers. Improved bus mastering allows portions of the total bandwidth to be permanently reserved for specific peripherals; this method is called isochronous data transmission(isochronous data transfer). The USB bus interface contains two main modules: serial interface machine(Serial Interface Engine - SIE), responsible for the bus protocol, and root hub(Root Hub), used to expand the number of USB bus ports.

The USB bus allocates 500 mA to each port. Thanks to this, low-power devices that would normally require a separate AC adapter can be powered via cable - USB allows the PC to automatically detect the required power and deliver it to the device. Hubs accept full power from the USB bus (bus powered), but may have their own AC converter. Self-powered hubs delivering 500 mA per port provide maximum flexibility for future devices. Port switching hubs isolate all ports from each other, so one that is shorted does not disrupt the operation of the others.

The USB bus promises a PC with a single USB port instead of today's four or five different connectors. You can connect one large powerful device to it, such as a monitor or printer, which will act as a hub, providing connectivity to other smaller devices, such as a mouse, keyboard, modem, scanner, digital camera, etc. However, this will require the development of special device drivers. However, this PC configuration has disadvantages. Some experts believe that the USB architecture is quite complex, and the need to support many different types of peripheral devices requires the development of a whole set of protocols. Others believe that the hub principle simply shifts cost and complexity from the system unit to the keyboard or monitor. But the main obstacle to USB's success is the IEEE 1394 FireWire standard.

IEEE 1394 FireWire bus

This high-speed peripheral bus standard was developed by Apple Computer, Texas Instruments and Sony. It was designed as a complement to the USB bus, not as an alternative to it, since both buses can be used in the same system, similar to modern parallel and serial ports. However, large digital camera and printer manufacturers are more interested in the IEEE 1394 bus than the USB bus because digital cameras are better suited to the 1394 socket rather than the USB port.

IEEE 1394 (commonly called FireWire) is much like USB, also a hot-swappable serial bus, but much faster. IEEE 1394 has two interface layers: one for the bus on the computer's motherboard and one for the point-to-point interface between the peripheral device and the computer over a serial cable. A simple bridge connects these two levels. The bus interface supports data transfer rates of 12.5, 25 or 50 MB/s, and the cable interface supports 100, 200 and 400 MB/s, which is much faster than the USB bus speed of 1.5 MB/s or 12 MB/s. The 1394b specification defines other ways to encode and transmit data, allowing speeds to increase to 800 Mb/s, 1.6 Gb/s or more. This high speed makes it possible to use IEEE 1394 to connect digital cameras, printers, TVs, network cards and external storage devices.

IEEE 1394 cable connectors are designed so that electrical contacts are located inside the connector housing, which prevents the possibility of electrical shock to the user and contamination of the contacts by the user's hands. These connectors are small and convenient, similar to the Nintendo GameBoy gaming connector, which has proven to have excellent durability. In addition, these connectors can be plugged blindly into the back of the PC. No terminal devices (terminators) and manual installation of identifiers are required.

The IEEE 1394 bus is designed for a 6-wire cable up to 4.5 m long, which contains two pairs of conductors for data transmission and one pair for powering the device. Each signal pair is shielded and the entire cable is also shielded. The cable allows voltages from 8V to 400V and currents up to 1.5A and maintains physical continuity of the device when the device is turned off or faulty (which is very important for a series topology). The cable provides power to devices connected to the bus. As the standard matures, the bus is expected to provide longer repeater-free distances and even greater throughput.

The basis of any IEEE 1394 connection is a microcircuit physical level and communication level, and the device requires two chips. The physical interface (PHY) of one device connects to the PHY of another device. It contains the circuits needed to perform the arbitration and initialization functions. The communication interface connects the PHY as well as the internal circuitry of the device. It transmits and receives packets in IEEE 1394 format and supports asynchronous or isochronous data transfers. The ability to support asynchronous and isochronous formats in the same interface allows non-time-critical applications such as scanners or printers, as well as real-time applications such as video and audio, to run on the bus. All physical layer chips use the same technology, while communication layer chips are specific to each device. This approach allows the IEEE 1394 bus to act as a peer-to-peer system, as opposed to the client-server approach of the USB bus. As a result, the IEEE 1394 system requires neither a serving host nor a PC.

Asynchronous transfer is the traditional way of transferring data between computers and peripheral devices. Here, data is transmitted in one direction and is accompanied by subsequent confirmation to the source. Asynchronous data transfer emphasizes delivery rather than performance. Data transfer is guaranteed and retransmissions are supported. Isochronous data transfer streams data at a predetermined rate so that the application can process it based on timing. This is especially important for time-critical media data, where just-in-time delivery eliminates the need for expensive buffering. Isochronous data transfers work on the principle of broadcasting, where one or more devices can “listen” to the transmitted data. The IEEE 1394 bus can simultaneously transmit multiple channels (up to 63) of isochronous data. Since isochronous transfers can take up a maximum of 80% of the bus bandwidth, there is sufficient bandwidth left for additional asynchronous transfers.

IEEE 1394's scalable bus architecture and flexible topology make it ideal for connecting high-speed devices, from computers and hard drives to digital audio and video equipment. Devices can be connected in a daisy chain or tree topology. The figure on the left shows two separate workspaces connected by an IEEE 1394 bus bridge. Workspace #1 consists of a video camera, a PC, and a VCR, which are all connected via IEEE 1394. The PC is also connected to a physically remote printer via a 1394 repeater, which increases the distance between the devices. amplifying bus signals. On an IEEE 1394 bus, up to 16 hops are allowed between any two devices. A 1394 splitter is used between the bridge and the printer to provide another port for connecting an IEEE 1394 bus bridge. Splitters provide users with greater topology flexibility.

Work area #2 contains only the PC and printer on bus segment 1394, as well as a connection to the bus bridge. A bridge isolates data traffic within each workspace. IEEE 1394 bus bridges allow selected data to be transferred from one bus segment to another. Therefore, PC #2 can request images from the VCR in work area #1. Since the bus cable also carries power, the PHY signal interface is always powered and data is transferred even if PC #1 is turned off.

Each IEEE 1394 bus segment allows the connection of up to 63 devices. Now each device can be located at a distance of up to 4.5 m; long distances are possible both with and without repeaters. Cable improvements will allow devices to be carried over longer distances. Bridges can connect over 1,000 segments, providing significant expansion potential. Another advantage is the ability to perform transactions at different speeds on a single medium per device. For example, some devices can run at 100 Mbps, while others can run at 200 Mbps and 400 Mbps. Hot swapping (connecting or disconnecting devices) on the bus is allowed even when the bus is fully operational. Changes in the bus topology are automatically detected. This eliminates the need for address switches and other user interventions to reconfigure the bus.

Thanks to packet transfer technology, the IEEE 1394 bus can be organized as if memory space is distributed between devices, or as if the devices are in slots on the motherboard. The device address consists of 64 bits, with 10 bits allocated for the network ID, 6 bits for the node ID, and 48 bits for memory addresses. As a result, 1023 networks of 63 nodes can be addressed, each with 281 TB of memory. Addressing memory rather than channels treats resources as registers or memory that can be accessed using processor-memory transactions. All this provides a simple network organization; For example, digital camera can easily transfer images directly to a digital printer without an intermediary computer. The IEEE 1394 bus shows that the PC is losing its dominant role in connecting the environment and it can be considered a very intelligent node.

The need to use two chips instead of one makes IEEE 1394 peripherals more expensive than SCSI, IDE, or USB peripherals, making it unsuitable for slow devices. However, its benefits for high-speed applications such as digital video editing make IEEE 1394 the primary interface for consumer electronics.

Despite the advantages of the IEEE 1394 bus and the appearance in 2000 of motherboards with built-in controllers for this bus, the future success of FireWire is not guaranteed. The advent of the USB 2.0 specification greatly complicated the situation.

USB 2.0 specification

Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC and Philips took part in the development of this specification, aimed at supporting high-speed peripheral devices. In February 1999, performance improvements of 10 to 20 times were announced, and in September 1999, engineering studies raised estimates to 30 to 40 times over USB 1.1. There have been concerns that with such performance, the USB bus will forever "bury" the IEEE 1394 bus. However, the general consensus is that the two buses are aimed at different applications. The goal of USB 2.0 is to provide support for all current and future popular PC peripherals, while IEEE 1394 is aimed at connecting consumer audio and video devices such as digital video recorders, DVDs and digital televisions.

According to USB 2.0, throughput increases from 12 Mb/s to 360-480 Mb/s. USB 2.0 is expected to be compatible with USB 1.1, providing users with a seamless transition to the new bus. New high-speed peripheral devices will be developed for it, which will expand the range of PC applications. Speeds of 12 MB/s are sufficient for devices such as phones, digital cameras, keyboards, mice, digital joysticks, tape drives, storage devices. floppy disk, digital speakers, scanners and printers. The increased bandwidth of USB 2.0 will expand the functionality of peripheral devices, providing support for high-definition cameras for video conferencing, as well as high-speed scanners and next-generation printers.

Existing USB peripherals will work unchanged in a USB 2.0 system. Devices such as keyboards and mice do not require the increased bandwidth of USB 2.0 and will function as USB 1.1 devices. The increased bandwidth of USB 2.0 will expand the range of peripheral devices that can be connected to a PC, and will also allow more USB devices to share the available bus bandwidth, up to the architectural limits of the USB bus. USB 2.0's backward compatibility with USB 1.1 could be a decisive advantage in the fight against the IEEE 1394 bus for the consumer device interface.

DeviceBay standard

DeviceBay is a new standard that follows on from the IEEE 1394 and USB bus standards. These buses allow devices to be connected and disconnected on the fly, i.e. during the operation of the PC. Such opportunity hot swap(hot swap, hot plug) required a new special connection between devices and the DeviceBay standard became the answer to this requirement. It standardizes bays into which hard drives, CD-ROM drives, and other devices can be inserted. The mounting frame is installed without tools and during PC operation. If the DeviceBay standard becomes widespread, it will do away with flat cables inside PC cases. The entire PC can be designed as a modular design, in which all modules are connected to USB buses or FireWire as DeviceBay devices. In this case, the device can be freely moved between the PC and other home devices.

The DeviceBay standard is designed to connect devices such as Zip drives, CD-ROM drives, tape drives, modems, hard drives, PC card readers, etc.

Modern computing systems are characterized by:

□ rapid growth in the speed of microprocessors and some external devices (for example, for displaying digital full screen video with high quality, a bandwidth of 22 MB/s is required);

□ the emergence of programs that require execution large quantity interface operations (for example, graphics processing programs in Windows, multimedia).

Under these conditions, the throughput of expansion buses serving several devices simultaneously was not enough for comfortable user experience, since computers began to “think” for a long time. Interface developers have taken the path of creating local buses connected directly to the MP bus, operating at the MP clock frequency (but not at its internal operating frequency) and providing communication with some high-speed devices external to the MP: main and external memory, video systems, etc. d.

There are currently three main universal local bus standards: VLB, PCI and AGP.

VLB bus(VL-bus, VESA Local Bus) introduced in 1992 by the Video Electronics Standards Association (VESA - a trademark of the Video Electronics Standards Association) and therefore is often called the VESA bus. The VLB bus is essentially an extension of the internal MP bus for communication with the video adapter and, less often, with hard drive, multimedia cards, network adapter. The bus width for data is 32 bits, for the address - 30, the actual data transfer speed via VLB is 80 MB/s, theoretically achievable - 132 MB/s (in version 2 - 400 MB/s).

Disadvantages of the VLB bus:

□ targeting only MP 80386, 80486 (not adapted for Pentium class processors);

□ strict dependence on the clock frequency of the MP (each VLB bus is designed only for a specific frequency up to 33 MHz);

□ small number of connected devices - only 4 devices can be connected to the VLB bus;

□ there is no bus arbitration - there may be conflicts between connected devices.

PCI bus(Peripheral Component Interconnect, connection of external components) is the most common and universal interface for connecting various devices. Developed in 1993 by Intel. The PCI bus is much more versatile than VLB; allows connection of up to 10 devices; has its own adapter, allowing it to be configured to work with any MP from 80486 to modern Pentium. PCI clock frequency is 33 MHz, bit width is 32 bits for data and 32 bits for addresses, expandable to 64 bits, theoretical throughput is 132 MB/s, and in the 64-bit version - 264 MB/s. Modification 2.1 of the local PCI bus operates at a clock frequency of up to 66 MHz and, at 64 bits, has a throughput of up to 528 MB/s. Supports Plug and Play, Bus Mastering and adapter auto-configuration modes.

Structurally, the bus connector on the system board consists of two consecutive sections of 64 contacts (each with its own key). Using this interface, video cards, sound cards, modems, SCSI controllers and other devices are connected to the motherboard. Typically, a motherboard has several PCI slots. The PCI bus, although local, also performs many of the functions of an expansion bus. Expansion buses ISA, EISA, MCA (and it is compatible with them), in the presence of a PCI bus, are connected not directly to the MP (as is the case when using the VLB bus), but to the PCI bus itself (via an expansion interface). Thanks to this solution, the bus is independent of the processor (unlike VLB) and can work in parallel with the processor bus without accessing it for requests. Thus, the processor bus load is significantly reduced. For example, the processor works with system memory or cache memory, and at this time information is written to the hard drive over the network. The PCI bus system configuration is shown in Fig. 5.8.

AGP bus(Accelerated Graphics Port - accelerated graphics port) - an interface for connecting a video adapter to a separate AGP trunk that has

Chapter 5. Microprocessors and motherboards

output directly to system memory. A bus based on the PCI v2.1 standard has been developed. The AGP bus can operate at system bus speeds up to 133 MHz and provides the highest graphics transfer rates. Its peak throughput in AGP4x quadruple multiplication mode (4 data blocks are transferred per clock cycle) is 1066 MB/s, and in AGP8x octal multiplication mode it is 2112 MB/s. Compared to the PCI bus, the AGP bus eliminates the multiplexing of address and data lines (in PCI, to reduce the cost of design, the address and data are transmitted over the same lines) and enhances the pipelining of read-write operations, which eliminates the impact of delays in memory modules on speed performing these operations.

Rice. 5.8. PCI System Configuration

The AGP bus has two operating modes: DMA And Execute. In DMA mode, the main memory is the video card memory. Graphic objects are stored in system memory, but are copied to the card's local memory before use. The exchange is carried out in large sequential packets. In Execute mode, system memory and local memory of the video card are logically equal. Graphic objects are not copied to local memory, but are selected directly from the system one. In this case, you have to select relatively small randomly located pieces from memory. Since system memory is allocated dynamically, in blocks of 4 KB, in this mode, to ensure acceptable performance, a mechanism is provided that maps sequential addresses of fragments to real addresses of 4 KB blocks in system memory. This procedure is performed using a special table (Graphic Address Re-mapping Table or GART) located in memory. The interface is designed as a separate connector into which an AGP video adapter is installed. The system configuration with the AGP bus is shown in Fig. 5.9.

In-machine system and peripheral interfaces

Rice. 5.9. System configuration with AGP bus

Everything said above regarding tires is summarized in table. 5.4. Table 5.4. Main characteristics of tires

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Local bus

All previously described tires have general disadvantage- relatively low throughput. This is due to the fact that the buses were designed with slow processors in mind. Subsequently, the processor speed increased, and the bus characteristics were improved mainly “extensively”, due to the addition of new lines. An obstacle to increasing the bus frequency was the huge number of boards released that could not operate at high communication speeds (this applies to MCA to a lesser extent, but for the reasons stated above, this architecture did not play a noticeable role in the market). At the same time, in the early 90s, changes occurred in the world of personal computers that required a sharp increase in the speed of exchange with devices:

• creation of a new generation of processors such as Intel 80486, operating at frequencies up to 66 MHz;
• increasing the capacity of hard drives and creating faster controllers;
• development and active promotion to the market graphical interfaces user (such as Windows or OS/2) have led to the creation of new graphics adapters that support more a high resolution and more colors (VGA and SVGA).

The obvious way out of this situation is the following: to carry out some of the data exchange operations that require high speeds, not through the I/O bus, but through the processor bus, approximately the same way as connecting external cache. This design is called a local bus. The figures clearly demonstrate the difference between conventional architecture and local bus architecture.

The local bus did not replace previous standards, but complemented them. The main buses in the computer were still ISA or EISA, but one or more local bus slots were added to them. Initially, these slots were used almost exclusively for installing video adapters, and by 1992, several incompatible local bus options had been developed, the exclusive rights to which belonged to the manufacturers. Naturally, such confusion held back the spread of local buses, so VESA (Video Electronic Standard Association) - an association representing more than 100 companies - proposed its local bus specification in August 1992.

VESA local bus (VL-bus)

The main characteristics of VL-bus are as follows.

• Support for 80386 and 80486 series processors. The bus is designed for use in single-processor systems, while the specification provides the ability to support x86-incompatible processors using a bridge chip.
• The maximum number of bus masters is 3 (not including the bus controller). If necessary, it is possible to install several subsystems to support a larger number of masters.
• Although the bus was originally designed to support video controllers, it can also support other devices (for example, hard disk controllers).
• The standard allows the bus to operate at frequencies up to 66 MHz, but the electrical characteristics of the VL-bus connector limit it to 50 MHz (this limitation, of course, does not apply to devices integrated into the motherboard).
• The bi-directional 32-bit data bus also supports 16-bit communication. The specification includes the possibility of 64-bit exchange.
• DMA support is provided only for bus masters. The bus does not support special DMA "initiators".
• The maximum theoretical bus bandwidth is 160 MV/sec (at a bus frequency of 50 MHz), the standard is 107 MV/sec at a frequency of 33 MHz.
• Supported batch mode exchange (for 80486 motherboards that support this mode). 5 lines are used to identify the type and speed of the processor, the Burst Last (BLAST#) signal is used to activate this mode. For systems that do not support this mode, the line is set to 0.
• The bus uses a 58-pin MCA connector. A maximum of 3 slots are supported (on some 50 MHz buses, only 1 slot can be installed).
• The VL-bus slot is installed in a line behind the ISA/EISA/MCA slots, so all lines of these buses are available to VL-boards.
• Both the integrated processor cache and the motherboard cache are supported.
• Supply voltage is 5 V. Devices with 3.3 V output are supported provided they can handle 5 V input.

The VL-bus was a huge improvement over the ISA in both performance and design. One of the advantages of the bus was that it allowed the creation of cards that worked with existing chipsets and did not contain a large number of expensive control logic circuits. As a result, VL cards were cheaper than similar EISA cards. However, this tire was not without its drawbacks, the main ones being the following.

• Orientation towards the 486th processor. VL-bus is hardwired to the 80486 processor bus, which is different from the Pentium and Pentium Pro/Pentium II buses.
• Limited performance. As already mentioned, the real VL-bus frequency is no more than 50 MHz. Moreover, when using processors with a frequency multiplier, the bus uses the main frequency (for example, for the 486DX2-66 the bus frequency will be 33 MHz).
• Circuit restrictions. The quality of signals transmitted over the processor bus is subject to very stringent requirements, which can only be met with certain load parameters for each bus line. According to Intel, installing insufficiently carefully designed VL boards can lead not only to data loss and synchronization problems, but also to system damage.
• Limitation on the number of boards. This limitation also arises from the need to comply with the load limits of each line.

Despite the existing shortcomings, VL-bus was the undoubted leader in the market, as it made it possible to eliminate the bottleneck in two subsystems at once - the video subsystem and the hard disk exchange subsystem. However, the leadership was short-lived, as Intel developed its new product - the PCI bus. According to the company, VL-bus was based on 11-year-old technologies and was just a “patch”, a compromise between manufacturers. True, VESA stated that both buses can “coexist” together in one system. Intel agreed that such a neighborhood was possible, but asked a counter-deadly question: “Why?” In fairness, it must be said that PCI was indeed freed from most of the disadvantages inherent in VL-bus.