Analog-to-digital converters (ADCs) are devices that receive analog signals and produce digital signals at the output, suitable for operation of computers and other digital devices. The conversion characteristic reflects the dependence of the output digital code from the input DC voltage. The transformation characteristic can be specified graphically, tabularly or analytically.

STATIC PARAMETERS

Intercode voltage– the point at which both adjacent code combinations are equally probable.

Quantization step– difference between adjacent values ​​of intercode transition voltages.

Zero offset voltage – parallel shift of the transformation characteristic relative to the abscissa axis.

Conversion factor deviation– error at the end of the transformation characteristic.

ADC non-linearity– Deviation of the actual value of the input voltage at a given point from the actual value determined by the linearized conversion characteristic at the same point. Expressed as a number of quantization steps or relative to the maximum input voltage as a percentage.

Differential nonlinearity– deviation of actual quantization steps from their average value.

DYNAMIC PARAMETERS OF ADC.

1. Sampling frequency - the frequency at which sample values ​​of the signal are generated, measured in the number of samples per second, or in hertz.

2. Conversion time – the time from the ADC start pulse or from the time of change in the analog input signal until a stable code appears at the output. For some ADCs this value depends on the input signal, for others it is constant. When working without UVH, this value is the aperture time.

3. Frequency error of the transmission coefficient - the error in the formation of sample values ​​when working with changing signals. Defined for a sinusoidal input signal. (For ADC K1107 PV2 8 bit, 80 MHz: P = 7 MHz at level 0.99).

4. Aperture time - the time during which uncertainty remains between the sample value and the time to which it refers. Consists of aperture shift and aperture uncertainty.

Depending on how the conversion process unfolds over time, ADCs are divided into:

1. Sequential

2. Parallel

3. Series - parallel.

SERIAL ADCs

ADC with step ramp voltage.

A positive voltage is supplied to the converter input. The counter is pre-set to zero, so the voltage at the DAC output is also 0. At the same time, logic 1 is set at the comparator output. The input of the 3I-NOT circuit receives pulses from the clock pulse generator. However, since log.0 is written to the R-S trigger, pulses do not pass to the counter input.

After the start pulse R-S trigger goes into a state with log.1 at the output and clock pulses begin to arrive at the counter input. The number recorded in the counter begins to increase and the voltage at the DAC output increases accordingly. At some point it is compared with the input voltage at the converter input, the comparator switches to log.0. and pulses stop arriving at the counter input. This signal from the comparator also arrives at the input of the RS trigger, switching it to the log.0 state at the output, which finally stops the conversion process. The resulting output code corresponds to the voltage at the low-order DAC output, or to the input analog signal with an accuracy of one. The process can then be repeated.

The minimum period of clock pulses can be found from the condition:

Cumin ≥ tcomp. + tdigit. + tDC + tRC, where:

tcomp – comparator response delay,

tdigits – counter delay,

tsap – DAC establishment time,

t RC – delay RC – chains.

Example. Let's calculate the conversion time of an ADC with 10 bits.

Elements used:

DAC – K572 PA1: number of bits N = 10, output voltage settling time tDC = 5 ∙ 10 -6 sec. At Vop = 10V quantization step

EMP = 10/(2 10 –1) = 10 mV.

COMPARATOR – 521 CA3 - at dV = 3 mV tcomp = 100 nsec.

We choose the time constant RC equal to 0.5 ∙ 10 -6 sec.

tdigit = 0.05 ∙ 10 -6 sec,

Cumin ≥ 0.1 + 0.05 + 5. 0 + 0.5 = 5.65 µs.

Maximum input signal measurement time:

(2 10 – 1) ∙ 5.65 ∙ 10 – 6 sec = 6 msec, sampling frequency is 160 Hz.

Aperture time – 6 ms.

ADCs of this type are used with UVH, or for converting slowly changing signals. The ADC error is determined by the accuracy parameters of the DAC used.

A variety of this type of ADC is tracking ADCs carry out the transformation continuously. They use an up/down counter and a comparator determines the direction of counting. At Vin< Vцап счетчик считает вверх, в при Vвх >The VDC counter counts down. Thus, the voltage Vdac constantly tends to be equal to Vin. The maximum input tracking speed is: dVin/dt< ЕМР/ Тмин.

Successive approximation ADC.

The procedure for determining the output code is determined by the successive approximation register. At the beginning, log.0 is written to all bits of the register. The voltage at the DAC output is zero. Next, log.1 is written to the most significant bit of the register. If output voltage In this case, the DAC is still less than the input voltage (log. 1 is set at the comparator output, then the value of the logical level in this bit is stored. If the voltage at the DAC output is greater than Vin., then this bit is reset to zero and then log. 1 is written to the next digit. In this way, the values ​​of all digits are determined, including the least significant. After this, a readiness signal is issued and the measurement cycle can be repeated.

This type of DAC has a speed advantage over the previous DAC, so it is the most widely used. Its conversion time is equal to Tmin ∙ N.

Tmin – the minimum value of the clock pulse repetition period is determined similarly to the previous DAC, N – the number of bits.

Example: the integrated ADC 1108 PV2 has all the elements on the chip: DAC, reference voltage source, successive approximation register, clock generator, comparator. N = 12, minimum conversion time - 2 µs.

DAC with time-pulse conversion (linear coding method).

An ADC of this type uses the conversion of the measured voltage into a time interval proportional to it, which is filled with pulses of a reference frequency. This time interval is formed by a sawtooth voltage generator (RVG) and a comparator. The number of pulses is considered a counter which determines the ADC output code.

The performance of such a circuit is higher than that of a DAC with a stepped sawtooth voltage, since it does not have a DAC and is determined by the performance of the comparator and counter. The comparator turn-off time is selected subject to the overexcitation that provides the necessary error in comparing the input signal and the sawtooth voltage.

To reduce errors, the reference frequency generator and the GPG must be mutually stable.

The ADC is described: N = 10, f etal = 100 MHz, t convert. = 10 µsec.

ADC with push-pull integration.

The disadvantage of the sequential ADCs discussed above is their relatively low noise immunity, which limits their resolution. An increase in the number of bits is associated with the use of high-precision DACs, which makes the production of such ADCs more expensive.

The principle of double integration in an ADC allows one to largely get rid of these shortcomings. Full cycle his work consists of two measures. In the first, the input voltage is integrated using an analog integrator over a fixed time interval T0. This time interval is formed by a counter, the input of which receives pulses from a generator with a frequency fsch.

Interval T0 is equal to:

Т0 = Nmax ∙ tсч

Here tcount = 1/fc is the frequency period of the clock generator, Nmax is the maximum counter capacity, which determines the resolution of the ADC.

The charge on capacitor C will then be equal to:

In the second cycle, the capacitor is discharged from the reference voltage source Vref. The polarity of the reference voltage is opposite to the polarity of the input signal, so the voltage across capacitor C begins to decrease. The counter counts the generator pulses at this time clock frequency fcount, starting from the zero state. At the point in time when the comparator passes through zero, counting stops and the number is written to the output register. The charge q2 that discharged the capacitor is equal to.

Significant difficulties arise when reducing the random error when measuring a time-varying quantity. At the same time, to obtain best estimate of the measured value, a filtering procedure is applied. Depending on the type of transformations used, linear and nonlinear filtering are distinguished, where the implementation of individual procedures can be carried out both in hardware and software.

Filtering can be used not only to suppress interference induced on the input transmission circuits analog signal, and, if necessary, to limit the spectrum of the input signal and restore the spectrum of the output signal (this was already discussed earlier). If necessary, filters with a tunable cutoff frequency can be used.

The use of automatic correction of systematic errors can be considered as adaptation of the channel to its own state. Application of modern element base allows today to implement input circuits that adapt to the characteristics of the input signal, in particular to its dynamic range. For such adaptation, an input amplifier with controlled gain is required. If, based on the results of previous measurements, it was possible to establish that the dynamic range of the signal is small compared to the range of the ADC input signal, then the amplifier gain is increased until the dynamic range of the signal corresponds to the operating range of the ADC. In this way, it is possible to minimize the signal sampling error and, consequently, increase the accuracy of measurements. The change in the signal gain at the input is taken into account in software when processing the measurement results by a digital controller.

Conformity assessment criteria dynamic range signal and the operating range of the ADC will be discussed further; methods for adapting the input channel to the frequency properties of the input signal will also be considered.

2.4. Sample-and-hold devices

When collecting information and its subsequent conversion, it is often necessary to fix the value of an analog signal for a certain period of time. For this purpose, sampling and storage devices (SSDs) are used. Another name for such devices is analog storage devices (AMD). Their work is carried out in two modes. In the sampling (tracking) mode, they must repeat the input analog signal at their output, and in the storage mode, they must store and output to their output the last input voltage preceding the moment the device switches to this mode.

In the simplest case, when constructing a UVH, to carry out these operations we only need a capacitor WITH XP and key S(Fig. 2.12. A). When the switch is closed, the voltage on the capacitor and at the output of the UVH will repeat the input. When the key is opened, the voltage on the capacitor, the value of which will be equal to the input voltage at the moment the key is opened, will be stored on it and transmitted to the output of the UVH.

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Rice. 2.12. Functional diagram of UVH ( A) and time diagrams of its operation ( b)

Obviously, in practical implementation, the voltage level on the capacitor in storage mode will not remain constant (Fig. 2.12. b) due to its discharge by current to the load and discharge due to its own leakage currents. In order to keep the capacitor voltage as long as possible acceptable level At the output of the UVH, a repeater is installed on the op-amp ( D.A. 1 in Fig. 2.12. A). As you know, a repeater has a high input impedance. This “decouples” the capacitor circuit and the load circuit in resistance and significantly reduces the discharge of the capacitor through the load. To reduce your own leakage currents, you need to choose a capacitor with a high-quality dielectric. And of course, in order for the voltage on the capacitor to remain constant for as long as possible, it is necessary to take as large a capacitance as possible.

When transferring the UVH from storage mode to tracking mode, the voltage on the capacitor will reach current level input voltage not immediately (Fig. 2.12. b). The time it takes for this to happen will be determined by the time it takes for the capacitor to charge - this time is called the acquisition time or sampling time. The capacitor will charge the faster, the greater its charge current. In order for this current not to be limited by the output resistance of the previous stage, a repeater is also installed at the input of the UVH at the op-amp ( D.A. 2 in Fig. 2.12. A). IN in this case The property that the repeater has a low output impedance is used. The capacitor will charge the faster the smaller its capacity. Thus, the conditions for choosing the capacitance value of the capacitor for optimal operation of the UVH in different modes are contradictory - the capacitance of the capacitor must be selected each time based on the specific requirements for the duration of its operating modes.

The input follower drives the capacitive load. Therefore, to build it, operational amplifiers are used that are stable at unity gain and a large capacitive load.

When using UVH in an ADC, the storage time, as a rule, is not much longer than the conversion time of the ADC. In this case, the capacitor value is selected in such a way as to obtain best time capture provided that the voltage drop during one conversion does not exceed the value of the least significant bit of the ADC.

Since dielectric losses in a storage capacitor are one of the sources of errors, it is best to choose capacitors with a dielectric made of polypropylene, polystyrene and Teflon. Mica and polycarbonate capacitors already have very mediocre characteristics. And you should not use ceramic capacitors at all.

The precision characteristics of the UVH include the zero offset voltage, which usually does not exceed 5 mV (if an op-amp with bipolar transistors is used at the input; op-amp with field effect transistors at the input, have a more significant zero offset) and the drift of the fixed voltage at a given capacity of the storage capacitor (for different UVHs from 10-3 to 10-1 V/s is normalized at the capacitance WITH XP = 1,000 pF). The amount of drift can be reduced by increasing the capacitance WITH HR. However, this degrades the dynamic characteristics of the circuit.

The dynamic characteristics of the UVH include: sampling time, which shows how long, under the most unfavorable conditions, the process of charging a storage capacitor with a given tolerance level lasts; and aperture delay - the period between the moment the control voltage is removed and the actual locking of the key.

There are many integrated circuits sampling-storage, having good characteristics. A number of circuits include an internal storage capacitor and guarantee maximum sampling times of tens or hundreds of nanoseconds with an accuracy of 0.01% for a 10 V signal. The aperture delay value for popular UVHs does not exceed 100 ns. If higher performance is required, hybrid and modular UVHs can be used.

As an example of the practical construction of the UVH in Fig. 2.13 is given functional diagram BIS K1100SK2 (LF398). The circuit has a common negative feedback, covering the entire circuit - from the output of the repeater to the operational amplifier D.A. 2 to the repeater input on the amplifier D.A. 1.

Dating" href="/text/category/datirovaniye/" rel="bookmark">dating the ADC reading when measuring a variable signal, in multi-channel measuring systems for simultaneous data collection from various sensors, eliminating high-frequency emissions in the DAC output signal when changing the code. These and other applications of UVC will be discussed in more detail in further material.

3. DIGITAL TO ANALOG CONVERTERS

3.1 General implementation methods

Digital-to-analog converters (DACs) are devices used to convert digital code into an analog signal in magnitude proportional to the value of the code.

DACs are widely used for connecting digital control systems with actuators and mechanisms that are controlled by the level of an analog signal, as components more complex analog-to-digital devices and converters.

In practice, DACs are mainly used for converting binary codes, so further discussion will only be about such DACs.

Any DAC is characterized, first of all, by its conversion function, which connects a change in the input value (digital code) with a change in the output value (voltage or current) Fig. 3.1.

Rice. 3.1. Conversion function (transfer characteristic) of DAC

Analytically, the DAC conversion function can be expressed as follows (for the case when the output signal is represented by voltage):

U OUT = ( U MAX / N MAX) N VX, where

U OUT – output voltage value corresponding to the digital code N VX supplied to the DAC inputs.

U MAX – maximum output voltage corresponding to the maximum code applied to the inputs N MAX.

Size TO DAC defined by the ratio U MAX/ N MAX is called the digital-to-analog conversion ratio. Its constancy for the entire range of changes in the arguments determines the proportionality of changes in the value of the output analog signal to the corresponding changes in the value of the input code. That is why, despite the stepwise nature of the characteristic associated with a discrete change in the input value (digital code), it is believed that DACs are linear converters.

If the value N The VX can be represented through the values ​​of the weights of its bits, the DAC conversion function can be expressed as follows:

U OUT = DAC, where

i– digit number of the input code N VX;

A i – value i th digit (zero or one);

U i – weight i-th category;

n– number of bits of the input code (number of bits of the DAC).

This method of recording the conversion function largely reflects the operating principle of most DACs, which essentially consists of summing the shares of an analog output value (summing analog measures), each of which is proportional to the weight of the corresponding digit.

In general, according to the construction method, DACs are distinguished with a weighted summation of currents, with a weighted summation of voltages, and based on a code-controlled voltage divider.

When constructing a DAC based on a weighted summation of currents in accordance with the values ​​of the bits of the input code N The VX signals from the current generators are summed and the output signal is represented by current. The construction of a four-bit DAC using this principle is illustrated in Fig. 3.2. The values ​​of the generator currents are selected proportional to the weights of the discharges binary code, i.e. if the current value of the smallest current generator corresponding to the least significant bit of the input code is equal to I, then the value of each next one must be twice as large as the previous one - 2 I, 4I, 8I. Every i th digit of the input code N VX controls i-th key S i. If i th rank equal to one, then the corresponding switch is closed and then the current of the generator, whose current value is proportional to the weight of this i th category, participates in the formation of the output current of the converter. Thus, it turns out that the output current is IN VH.

Rice. 3.2. Construction of a DAC based on weighted summation of currents

N S 1, S 2 and S 4 in the diagram in Fig. 3.2 will be closed, and the key S 3 – open. Thus, currents equal to I, 2I and 8 I. In total they will form the output current IEXIT = 11I, i.e. the value of the output current I N VX = 11.

When constructing a DAC based on a weighted summation of voltages in accordance with the values ​​of the bits of the input code N The I/O output signal of the DAC is formed from the values ​​of the voltage generators and is represented by voltage. The construction of a four-bit DAC using this principle is illustrated in Fig. 3.3. The values ​​of the voltage generators are set in accordance with the binary distribution law - proportional to the weights of the bits of the binary code ( E, 2E, 4E and 8 E). If i th digit of the input code N BX is equal to one, then the corresponding switch must be open, and a voltage generator whose voltage value is proportional to the weight of this i-th category, participates in the formation of the output voltage U converter OUT. Thus, it turns out that the output voltage is U DAC OUTPUT is proportional to input code size N VH.

Rice. 3.3. Construction of a DAC based on weighted summation of voltages

For example, if the input code value N BX is equal to eleven, i.e. in binary form it is represented as (1011), then the keys controlled by the corresponding bits S 1, S 2 and S 4 in the diagram in Fig. 3.3 will be open, and the key S 3 – closed. Thus, voltages equal to E, 2E and 8 E. In total they will form the output voltage U OUT = 11 I, i.e. the value of the output voltage U OUT will be proportional to the value of the input code N VX = 11.

In the latter case, the DAC is implemented as a code-controlled voltage divider (Fig. 3.4).

Rice. 3.4. Construction of a DAC based on a code-controlled voltage divider

The code-controlled divider consists of two arms. If the bit width of the implemented DAC is equal to n, then the number of resistors in each arm is 2 n. The resistance of each arm of the divider is changed using keys S. The keys are controlled by the output unitary code of the decoder DC, and the keys of one arm are controlled directly by it, while the others are controlled through inverters. The output code of the decoder contains a number of units equal to the value of the input code N VH. It is not difficult to understand that the division coefficient of the divider will always be proportional to the value of the input code N VH.

Two latest methods have not found widespread use due to practical difficulties in their implementation. For a DAC structure with weighted summation of voltages, it is impossible to implement voltage generators that would allow the mode short circuit at the output, as well as switches that do not have residual voltages in the closed state. In a DAC structure based on a code-controlled divider, each of the two divider arms consists of very large number resistors (2 n), includes the same number of keys for managing them and a large decoder. Therefore, with this approach, the implementation of the DAC turns out to be very cumbersome. Thus, the main structure used in practice is the current-weighted summation DAC structure.

3.2 DAC with weighted current summation

Let's consider the construction of a simple DAC with weighted summation of currents. In the simplest case, such a DAC consists of a resistive matrix and a set of switches (Fig. 3.5).

Rice. 3.5. Resistive matrix DAC implementations

The number of keys and the number of resistors in the matrix is ​​equal to the number of bits n input code N VH. Resistor values ​​are chosen proportional to the weights of the binary code, i.e. proportional to the values ​​of the series 2i,i = 1… n. When a voltage source is connected to a common node of the matrix and the keys are closed, current will flow through each resistor. The current values ​​of the resistors, thanks to the appropriate choice of their values, will be distributed according to the binary law, i.e., proportional to the weights of the bits of the binary code. When submitting an entry code N VX keys are switched on in accordance with the value of the corresponding bits of the input code. The key is closed if the corresponding bit is equal to one. In this case, in the current node, currents are summed up, proportional to the weights of these bits, and the magnitude of the current flowing from the node as a whole will be proportional to the value of the input code N VH.

In such a structure there are two output nodes. Depending on the value of the bits of the input code, the corresponding keys are connected to the node connected to the output of the device, or to another node, which is most often grounded. In this case, current flows constantly through each resistor of the matrix, regardless of the position of the switch, and the amount of current consumed from the reference voltage source is constant.

Rice. 3.6. Implementations of a DAC based on a resistive matrix and with switches

A common disadvantage of both structures considered is the large ratio between the smallest and largest values ​​of the matrix resistors. At the same time, despite the large difference in resistor ratings, it is necessary to ensure the same absolute error in fitting both the largest and the smallest resistor rating. That is, the relative accuracy of fitting large resistors should be very high. In an integrated DAC design with a number of bits of more than ten, this is quite difficult to achieve.

Structures based on resistive materials are free from all these disadvantages. R- 2R matrices (Fig. 3.7).

Rice. 3.7. DAC based implementations R-2R resistive matrix

and with switch keys

You can verify that with this construction of the resistive matrix, the current in each subsequent parallel branch is two times less than in the previous one, i.e. their values ​​are distributed according to a binary law. The presence in the matrix of only two resistor values, differing by a factor of two, makes it possible to quite simply adjust their values, without making high demands on the relative accuracy of the adjustment.

3.3 DAC parameters and errors

The system of electrical characteristics of DACs, reflecting the features of their construction and operation, combines more than a dozen parameters. Below are the main ones, recommended for inclusion in the regulatory and technical documentation as the most common and most fully describing the operation of the converter in static and dynamic modes.

1. Number of bits – number of bits of the input code.

2. Conversion coefficient - the ratio of the output signal increment to the input signal increment for linear function transformations.

3. The settling time of the output voltage or current is the time interval from the moment of a given code change at the input of the DAC until the moment at which the output voltage or current finally enters a zone with a width equal to the weight of the least significant bit (LSB), symmetrically located relative to the steady-state value. In Fig. Figure 3.8 shows the transition function of the DAC, showing the change in the DAC output signal over time when the code changes. In addition to the settling time, it also characterizes some other dynamic parameters of the DAC - the amount of output signal overshoot, the degree of damping, circular frequency establishment process, etc. When determining the characteristics of a particular DAC this characteristic is removed when the code changes from a zero value to a code equal to half of it maximum value.

4. Maximum conversion frequency – highest frequency discretization, in which the specified parameters comply with established standards.

There are other parameters that characterize the performance of the DAC and the features of its functioning. These include: input voltage low and high level, output leakage current, consumption current, output voltage or current range, influence factor of instability of power supplies and others.

The most important parameters for a DAC are those that determine its accuracy characteristics, which are determined by errors normalized by magnitude.

Rice. 3.8. Determining the settling time of the DAC output signal

First of all, it is necessary to clearly distinguish static and dynamic errors DAC. Static errors are the errors that remain after the completion of all transient processes associated with changing the input code. Dynamic errors are determined by transient processes at the output of the DAC or its composite units arising as a result of a change in the input code.

The main types of static DAC errors are defined as follows.

Absolute conversion error at scale end point– deviation of the output voltage (current) value from the nominal value corresponding to the end point of the conversion function scale. For DACs operating with an external reference voltage source, it is determined without taking into account the error introduced by this source. Measured in units of the least significant digit of the conversion.

Zero offset voltage at the output – the voltage at the output of the DAC with a zero input code. Measured in low order units. Determines the parallel shift of the actual transformation function and does not introduce nonlinearity. This is an additive error.

Conversion factor error(scale) – multiplicative error associated with the deviation of the slope of the transformation function from the required one.

DAC non-linearity– deviation of the actual transformation function from the specified straight line. The main requirement for a DAC from this point of view is the mandatory monotonicity of the characteristic, which determines the unambiguous correspondence between the output and input signals of the converter. Formally, the requirement of monotonicity is the constancy of the characteristic sign of the derivative throughout the entire working area.

Nonlinearity errors are generally divided into two types - integral and differential.

Integral nonlinearity error– maximum deviation of the actual characteristic from the ideal one. In fact, this considers the averaged transformation function. This error is determined as a percentage of the final range of the output value. Integral nonlinearity arises due to various nonlinear effects that affect the operation of the converter as a whole. They are most clearly manifested in the integrated design of converters. For example, it may be associated with different heating levels in the LSI of some nonlinear resistances for different input codes.

Differential nonlinearity error– deviation of the actual characteristic from the ideal one for adjacent code values. These errors reflect non-monotonic deviations of the actual characteristics from the ideal ones. To characterize the entire transformation function, the local differential nonlinearity with the maximum absolute value is selected. Limits acceptable values differential nonlinearity are expressed in units of the weight of the least significant digit.

Let's consider the reasons for the appearance of differential errors and how they affect the DAC conversion function. Let's imagine that all the weights of the bits in the DAC are set perfectly accurately, except for the weight of the most significant bit.

If we consider the sequence of all code combinations for a binary code of a certain bit depth, then the patterns of binary code formation determine, among other things, that in code combinations corresponding to values ​​from zero to half the full scale (from zero to half the maximum code value), the most significant bit is always is equal to zero, and in code combinations corresponding to values ​​from half the scale to its full value, the most significant digit is always equal to one. Therefore, when applying codes corresponding to the first half of the input code value scale to the DAC, the weight of the most significant digit does not participate in the formation of the output signal, and when applying codes corresponding to the second half, it is constantly involved. But if the weight of this digit is specified with an error, then this error will also be reflected in the formation of the output signal. Then this will be reflected in the DAC conversion function, as shown in Fig. 3.9. A.

Rice. 3.9. Influence of reference error on the DAC conversion function

weights of the senior category.

From Fig. 3.9. A. it can be seen that for the first half of the input code values, the real DAC conversion function corresponds to the ideal one, and for the second half of the input code values, the real conversion function differs from the ideal one by the amount of error in setting the weight of the most significant bit. Minimizing the influence of this error on the DAC conversion function can be achieved by choosing a conversion scale factor that will reduce the error at the end point of the conversion scale to zero (Fig. 3.9. b). It is clear that the differential errors are distributed symmetrically relative to the middle of the scale. This determined another name for them - symmetrical type errors. At the same time, it is clear that the presence of such an error determines the non-monotonic behavior of the DAC conversion function.

In Fig. 3.10. A. It is shown how the real DAC conversion function will differ from the ideal one, provided that there are no errors in setting the weights of all digits except the digit preceding the most significant one. Rice. 3.10. b. shows the behavior of the transformation function if the scale component of the total error is selected (reduced to zero).

Metrology" href="/text/category/metrologiya/" rel="bookmark">it is rational to achieve metrological indicators in a comprehensive manner, using technological techniques with various structural methods. And when using ready-made integrated converters, structural methods are the only way to further improve the metrological characteristics of the conversion system .

Zero offset error and scale error are easily corrected at the DAC output. To do this, a constant offset is introduced into the output signal, compensating for the offset of the converter characteristic. The required conversion scale is established either by adjusting the gain set at the output of the amplifier converter, or by adjusting the value of the reference voltage if the DAC is a multiplying one.

Preface
Chapter 1. Features of the construction of high-speed DAC, ADC microcircuits and equipment for measuring them electrical parameters
1.1. Features of construction and design of the DAC
1.2. Features of the construction and design of the ADC
1.3. Features of constructing equipment for measuring electrical parameters of DAC and ADC
Chapter 2. Parameters of DAC and ADC chips and their definitions
2.1. General concepts
2.2. DAC Static Parameters
2.3. DAC Dynamic Parameters
2.4. ADC static parameters
2.5. Dynamic ADC parameters
Chapter 3. Construction schemes and electrical characteristics DAC chips
3.1. Twelve-bit DAC K594PA1 with settling time of 3.5 μs
3.2. Ten-bit DACs KM1118PA2, KR1 118PA2 with settling time 50 ns
3.3. Eight-bit DACs KP18PA1, KM1118PA1 with settling time 20 ns
3.4. Eight-bit DAC K1118PAZ with settling time 10 ns
Chapter 4 Construction schemes and electrical characteristics of ADC microcircuits
4.1. Six-bit ADC K1Yu7PV1 with a conversion frequency of 20 M1ts
4.2. Six-bit ADCs KP07PVZ with conversion frequency of 100 and 50 MHz
4.3. Eight-bit ADC K1107PV2 with a conversion frequency of 20 MHz
4.4. Eight-bit ADCs KP07PV4 with conversion frequency of 100 and 60 MHz
Chapter 5. Methods and equipment for measuring static and dynamic parameters, DAC chips
5.1. Methods for measuring static DAC parameters
5.2. Equipment for measuring static parameters of the DAC
5.3. Methods for measuring dynamic parameters of DACs
5.4. Equipment for measuring the settling time of a DAC
5.5. Switching circuits for DACs K594PA1, K1P8PA1, K1118PA2, KP8PAZ, K1118PA4 when measuring the settling time and features of their design
Chapter 6. Methods and equipment for measuring static and dynamic parameters of ADC chips
6.1. Methods for measuring static parameters of ADCs
6.2. Equipment for measuring static parameters of ADCs
6.3. Methods of measurement and principles of construction of meters for dynamic parameters of ADCs
6.4. Equipment for measuring dynamic parameters of ADCs
6.5. Connection circuits for the KP07 ADC IC when measuring dynamic parameters and features of their design
Chapter 7. Main functional units of dynamic parameters meters of DAC and ADC microcircuits
7.1. Time Interval Meters
7.2. Contact heads for measuring dynamic IC parameters
7.3. Test pulse generators
7.4. IC packages and their parasitic design parameters
7.5. DAC output amplifiers
7.6. Adapter boards
Chapter 8 Features of measurement and equipment for monitoring the electrical parameters of DAC and ADC microcircuits during their manufacture
8.1. Wafer inspection
8.2. Functional fit
8.3. Monitoring and measuring IC parameters over a temperature range
8.4. Electrothermal training
Chapter 9. Prospects for the development of high-speed DAC and ADC microcircuits and measurement of their parameters
9.1. Ways to increase the speed and capacity of the ADC
9.2. Ways to increase the speed and bit capacity of the DAC
9.3. Ways to increase the accuracy and bandwidth of electrical parameters meters DAC and ADC

Exist various methods compensation of static DAC errors. The main classification feature of methods is the class of errors taken into account. On this basis, the following methods are distinguished:

1. Correction of the scale and zero point of the characteristic;

2. Correction of deviation of switched measures;

3. Correction of general nonlinearity (both integral and differential).

First of all, error correction is carried out during the manufacture of converters (technological adjustment). However, it is often desirable when using a specific LSI sample in a particular device. In the latter case, correction is carried out by introducing into the structure of the device, in addition to the LSI DAC additional elements, i.e. at the structural level. As a result, such methods are called structural.

The DAC includes various functional units. When making adjustments, each of the nodes is adjusted independently of the others. The fitting algorithm must, first of all, ensure the monotonicity of the transformation function, then its linearity, the absence of zero offset and the required transformation coefficient.

The most difficult process is to ensure monotony and linearity, because they are determined by the related parameters of many elements and nodes. Most often, only the zero offset, conversion coefficient and differential nonlinearity of the symmetric type are adjusted, i.e. nonlinearity caused by errors of the divider and that part of the errors of the keys that can be reduced to errors of this kind. The rest of the errors are of a superpositional nature, i.e. manifest themselves in the mutual influence of elements on each other. It is very difficult to identify, control and correct such errors.

The accuracy parameters provided by technological methods deteriorate when the converter is exposed to various destabilizing factors, primarily temperature. It is also necessary to remember about the aging factor of elements.

As accuracy increases, the costs of converter development and manufacturing always increase. Taking all this into account, it is rational to improve metrological indicators in a comprehensive manner, using technological techniques with various structural methods. And when using ready-made integrated converters, structural methods are the only way to further improve the metrological characteristics of the conversion system.

Zero offset error and scale error are easily corrected at the DAC output. To do this, a constant offset is introduced into the output signal, compensating for the offset of the converter characteristic. The required conversion scale is established either by adjusting the gain set at the output of the amplifier converter, or by adjusting the value of the reference voltage if the DAC is a multiplying one.

Among the structural methods of characteristic linearization, it is necessary to highlight compensation methods and methods with control by a test signal.

Correction methods with test control consist of identifying DAC errors across the entire set of permissible input influences and adding corrections calculated on the basis of this to the input or output value to compensate for these errors.

For any correction method with control using a test signal, the following actions:

1. Measuring the characteristics of the DAC on a set of test influences sufficient to identify errors.

2. Identification of errors by calculating their deviations from measurement results.

3. Calculation of corrective amendments for the converted values ​​or the required corrective effects on the corrected blocks.

4. Carrying out correction.

The first three points relate to the control process, the last point - to the transformation process, because correction is carried out during conversion.

Control can be carried out once before installing the converter into the device using special laboratory measuring equipment. It can also be carried out using specialized equipment built into the device. In this case, monitoring, as a rule, is carried out periodically, all the time while the converter is not directly involved in the operation of the device. This ensures long-term metrological stability of the converter even when it is constantly exposed to any destabilizing factors. Such organization of control and correction of converters can be carried out when it operates as part of a microprocessor measuring system.

The simplest model The nonlinear component of the DAC error is based on the assumption of stability of the error for each code and its random dependence on the code. Obviously, identifying the parameters of such a model requires measuring the output signal on all valid codes (end-to-end control method). The use of a precision meter is mandatory for this method.

The main disadvantage of any end-to-end testing method is the long testing time along with the heterogeneity and large volume of equipment used.

A large group of control methods using a test signal is based on the assumption that the weights of the bits are independent of the code being converted. In this case, it is possible to create a system of independent equations, the number of which is equal to the number of corrected digits of the converter. Often this system of equations is added by two more, which determine the zero offset error and the scale error. To compose each equation, a code from a given set is supplied to the input of the converter. After resolving such a system of equations, it is possible to find the errors in setting each digit, and, consequently, the correction (compensating) value for each value of the input code. Such methods are currently most widespread and are used in the construction of microprocessor control systems.

The correction values ​​determined in one way or another are stored, as a rule, in digital form. Correction of errors, taking into account these corrections, can be carried out both in analog and digital form.

With digital correction, corrections are added taking into account their sign to the DAC input code. As a result, a code is received at the DAC input, which generates the required voltage or current value at its output. The simplest implementation of this correction method consists of a correctable DAC, at the input of which a digital memory is installed (Fig. 17.a). The input code plays the role of an address code. The memory at the corresponding addresses contains pre-calculated, taking into account corrections, code values ​​supplied to the corrected DAC.

Rice. Digital (a) and analogue (b) DAC error correction

For analog correction (Fig. 17.b), in addition to the main DAC, another additional DAC is used. The range of its output signal corresponds to the maximum error value of the corrected DAC. The input code is simultaneously sent to the inputs of the corrected DAC and to the address inputs of the correction memory. The corresponding one is selected from the memory of amendments given value input code correction. The correction code is converted into a signal proportional to it, which is summed with the output signal of the corrected DAC. Due to the smallness of the required range of the output signal of the additional DAC compared to the range of the output signal of the corrected DAC, the first’s own errors are neglected.

In some cases, it becomes necessary to correct the dynamics of the DAC.

The transient response of the DAC will be different when changing different code combinations, in other words, the settling time of the output signal will be different. Therefore, the maximum settling time must be taken into account when using a DAC. However, in some cases it is possible to correct the behavior of the transfer characteristic.

Let us set the conversion time to be less than the maximum settling time. If it is possible to identify the dynamic parameters of the DAC, it is possible to calculate such corrections to the input code of the DAC, at which the output value for this specified time will reach required value. At this moment, it is necessary to record the result of the conversion of the system nodes following the DAC, since after this moment the output signal of the DAC will continue to change, and reach a level corresponding not to the input code, but to its corrected value.

With a sequential increase in the values ​​of the input digital signal D(t) from 0 to 2N-1 through the least significant unit (EMP), the output signal U out (t) forms a stepped curve. This dependence is usually called the DAC conversion characteristic. In the absence of hardware errors, the midpoints of the steps are located on the ideal straight line 1 (Fig. 22), which corresponds to the ideal transformation characteristic. The actual transformation characteristic may differ significantly from the ideal one in terms of the size and shape of the steps, as well as their location on the coordinate plane. There are a number of parameters to quantify these differences.

Static parameters

Resolution- increment Uout when converting adjacent values ​​Dj, i.e. different on the EMR. This increment is the quantization step. For binary conversion codes, the nominal value of the quantization step is h=U psh /(2N-1), where U psh is the nominal maximum output voltage of the DAC (full scale voltage), N is the bit capacity of the DAC. The higher the bit depth of the converter, the higher its resolution.

Full scale error- the relative difference between the real and ideal values ​​of the conversion scale limit in the absence of a zero offset.

It is the multiplicative component of the total error. Sometimes indicated by the corresponding EMP number.

Zero offset error- the value of Uout when the DAC input code is zero. It is an additive component of the total error. Typically stated in millivolts or as a percentage of full scale:

Nonlinearity- maximum deviation of the actual conversion characteristic U out (D) from the optimal one (line 2 in Fig. 22). The optimal characteristic is found empirically so as to minimize the value of the nonlinearity error. Nonlinearity is usually defined in terms of relative units, but is also given in the reference data in the EMR. For the characteristics shown in Fig. 22.

Differential nonlinearity is the maximum change (taking into account the sign) of the deviation of the real transformation characteristic Uout(D) from the optimal one when moving from one input code value to another adjacent value. Usually defined in relative units or in EMP. For the characteristics shown in Fig. 22,

The monotonicity of the conversion characteristic is an increase (decrease) in the DAC output voltage Uout with an increase (decrease) in the input code D. If the differential nonlinearity is greater than the relative quantization step h/Upsh, then the converter characteristic is non-monotonic.

The temperature instability of a DA converter is characterized by the temperature coefficients of full scale error and zero offset error.

Full scale and zero offset errors can be corrected by calibration (tuning). Nonlinearity errors by simple means cannot be eliminated.

Dynamic parameters

The dynamic parameters of the DAC are determined by the change in the output signal when the input code changes abruptly, usually from the value “all zeros” to “all ones” (Fig. 23).

Settling time- time interval from the moment the input code changes (in Fig. 23 t=0) until the last time the equality is satisfied

|U out - U psh |= d/2,

Slew rate - maximum speed changes in Uout(t) during the transient process. It is defined as the ratio of the increment D Uout to the time t during which this increment occurred. Usually indicated in technical specifications DAC with voltage output. For a DAC with a current output, this parameter largely depends on the type of output op-amp.

For multiplying DACs with voltage output, the unity gain frequency and power bandwidth are often specified, which are mainly determined by the properties of the output amplifier.

DAC noise

Noise at the DAC output can appear for various reasons caused by physical processes occurring in semiconductor devices. To assess the quality of a high-resolution DAC, it is customary to use the concept of root mean square noise. They are usually measured in nV/(Hz) 1/2 in a given frequency band.

Surges (pulse noise) are sharp short spikes or dips in the output voltage that occur during a change in output code values ​​due to the non-synchronism of opening and closing analog switches in different bits of the DAC. For example, if, when moving from the code value 011...111 to the value 100...000, the key of the most significant digit of the D-A converter with the summation of weight currents opens later than the keys of the lower digits close, then a signal will exist at the DAC output for some time, corresponding to code 000...000.

Overshoot is typical for high-speed DACs, where capacitances that could smooth them out are minimized. A radical way to suppress emissions is to use sample-and-hold devices. Emissions are assessed by their area (in pV*s).

In table 2 shows the most important characteristics of some types of digital-to-analog converters.

table 2

DAC name	Digit capacity, bit	Number of channels	Output type	Setup time, µs	Interface	Internal ION	Voltage power supply, V	Power consumption mW	Note
Wide range of DACs
572PA1	10	1	I	5	-	No	5; 15	30	On MOS switches, multiplying
	10	1	U	25	Last	Eat	5 or +/-5	2
594PA1	12	1	I	3,5	-	No	+5, -15	600	On current switches
MAX527	12	4	U	3	Parall.	No	+/-5	110	Loading input words via 8-pin bus
DAC8512	12	1	U	16	Last	Eat	5	5
	14	8	U	20	Parall.	No	5; +/-15	420	On MOS switches, with an inverse resistive matrix
	8	16	U	2	Parall.	No	5 or +/-5	120	On MOS switches, with an inverse resistive matrix
	8	4	-	2	Last	No	5	0,028	Digital potentiometer
Micropower DACs
	10	1	U	25	Last	No	5	0,7	Multiplying, in an 8-pin package
	12	1	U	25	Parall.	Eat	5 or +/-5	0,75	Multiplying, consumption - 0.2 mW in economy mode
MAX550V	8	1	U	4	Last	No	2,5:5	0,2	Consumption 5 µW in economy mode
	12	1	U	60	Last	No	2,7:5	0,5	Multiplying, SPI-compatible interface
	12	1	I	0,6	Last	No	5	0,025	Multiplying
	12	1	U	10	Last	No	5 or 3	0.75 (5 h) 0.36 (3 h)	6-pin package, consumption 0.15 μW in economy mode. I 2 C-compatible interface
Precision DACs