Instructions for updating the software of receivers models DRE-4500, DRS-4500 and DRE-5500. (for subscribers of Tricolor TV-Siberia)

From April 22, 2014, an update will be launched for Tricolor TV-Siberia subscribers software(software) for receivers of the DRE-4500, DRS-4500 and DRE-5500 models, after which you will be able to watch Tricolor TV channels from the new Express-AT1 satellite.

Before starting the update, write down the current software version by going to the “Status” item in the main menu of the receiver.

Once the update is complete, the receiver software version should change to 2.2.215. New software will be downloaded from the air.

To update the receiver software, follow these steps:
1. Unplug the receiver's power cord from the outlet, and then plug the receiver back in.
2. Switch the receiver to the TV channel “Infochannel “Tricolor TV” (until the update is completed, this channel will be located at No. 9 (10) in the list, or in the place of the TNT channel).

After a few seconds, the following message will appear on the screen indicating the need to update the receiver software:

When of this message select the “YES” option and press the “OK” button on the remote control.

3. After agreeing to the update, service messages about the process of updating the receiver software will begin to appear on the screen. The type of messages is shown below. The software update takes about five minutes.

Attention! During the software update, do not turn off the power to the receiver! Otherwise, the receiver may fail!

4. Once the software update is complete, you will be prompted to press the “OK” button on the receiver’s remote control to reboot the receiver.

5. After rebooting, the receiver will turn on in the “Setup Wizard” mode. In a few steps, you will be asked to select the menu language, configure video output, search for Tricolor TV-Siberia TV channels and configure the display of time and time zone.

6. After completing the “Installation Wizard”, you can make sure that the receiver software version has changed to 2.2.215. To do this, go to “Menu”, select “Status” and check the value in the “Software version” line:

7. If the software version remains unchanged, you need to turn off and turn on the receiver on the Tricolor TV Infochannel channel and repeat the software update procedure.

8. This completes the receiver software update. The receiver is ready for further operation.

If the software update fails, download the firmware for Tricolor TV Siberia receivers from ours.

From February 3, 2016, new software will be launched for receiving equipment models DRE-4000, DRE-5000, DRS-5001, DRS-5003, as well as DRE-7300 and GS-7300, aimed at improving and improving the operation of this receiving equipment.

Before starting the update, go to the “Status” menu item and make sure that Current version receiver software is equal to 3.4.369 . If your receiver has a software version different from the one specified, the update cannot be guaranteed to be correct.

After performing the update, the receiver software version should change to 3.4.432 .

ATTENTION! Do not turn off the power to the receiver until the update procedure is completed! Otherwise, the receiver may fail!

To update the receiver and module software, you must perform the following steps:

1. Unplug the receiver's power cord from the outlet, and then plug the receiver back in.
2. Switch the receiver to the Tricolor TV info channel.
3. After a few seconds, the following message will appear on the screen indicating the need to update the receiver software:

Rice. 1
When this message appears, select the “Yes” option and press the “OK” button on the remote control.

4. After agreeing to update the receiver software, service messages about the process of updating the receiver software will appear on the screen. Updating the receiver software takes about three minutes.

5. Once the software update is complete, the receiver will reboot and turn on in channel viewing mode.

6. After the software update is completed, go to the “Status” menu and make sure that the receiver software version has changed to 3.4.432.

Rice. 4
7. At this point, the receiver software update is completed, and the receiver is ready for further operation.

Continuation

Schematic diagram of the main board MV-08 rev. 1.02, used in the DRS-4500 receiver, is very similar to the DRE-4500 receiver circuit board presented in the previous issue. Therefore, only the most different first part is shown here - Fig. 4.1. The differences in the remaining parts of the circuits are listed in Table. 1.

The DRE-4500 receiver uses the BS2F7VZ0194A NIM module manufactured by Sharp. One of the areas of her activity is the development of NIM and HALF-NIM modules for receivers of DVB-S/S2/CA ABS-S, ATSC, ISDB-T, DTMB standards and for digital TVs. Appearance module is shown in Fig. 5, and the view without the shielding cover is in Fig. 6. The installation of widely used microcircuits in it made it possible to create a high-quality device that was used in a huge number digital receivers various global manufacturers. The module is currently out of production.

The block diagram of the module is shown in Fig. 7. The signal from the external downconverter is supplied through the input F-connector to a compensating amplifier assembled on a 2SC5753 microwave transistor from California Eastern Laboratories. Boosted signal branches off to the LOOP output connector of the module for connecting additional receiver. At the same time, it comes to the RF converter with a “zero” IF, made on the IX2476VA chip (manufacturer’s marking on the case is B0010). It includes an AGC system, I and Q mixers with software-controlled low-pass filters, and a local oscillator with a PLL loop. The microcircuit works with input digital signals DVB-S standard in the frequency range 950...2150 MHz, transmitted with symbol rate from 1 to 45 Msimv/s.

An adjustable amplifier is included at the input of the microcircuit, providing a wide range of adjustment for working with input signals of various levels. The monolithic local oscillator has low levels of spurious emissions, and its frequency is stabilized by a crystal oscillator and a PLL loop. Oscillations of the reference frequency via a buffered output synchronize the QPSK demodulator. The RF converter devices are controlled via the 12C interface from Philips (NXP) from the receiver's control processor through the 12C repeater (repeater), which is part of the QPSK demodulator. The IX2476VA chip is produced in a 48-pin TQFP package.

The I and Q component signals from the output of the IX2476VA chip are fed to the ADC in the STV0299B QPSK demodulator. A dual ADC converts them into six-bit digital form with a sampling rate of up to 90 MHz. The chip, in addition to the DVB-S standard, allows you to decode signals of the DSS (DIRECTV™) standard. Therefore, the digitized signals after the interpolator pass through a digital cosine-square Nyquist filter with rounding factors of 0.35 and 0.2.

The demodulator has two loops digital AGC. The first of them controls the gain of the input RF converter, and the second affects the internal actuator circuits.

From the received signal, clock pulses are restored, which synchronize the operation of the nodes for converting QPSK signals into the TS transport stream. The microcircuit, using the input and output port located in its composition, can provide switching of the converter power supply and receiving ranges, as well as inject DiSEqC system signals into the reduction cable. However, this NIM module does not use such a function. The converter power supply in the figure is shown conditionally and is not included in the modules. It is assembled on a separate specialized chip in the DRE-4500 receiver and on discrete elements in the DRS-4500.

Parameters for receiving QPSK signals are set via the 12C bus, serviced by the receiver processor and operating at frequencies up to 4 MHz. The microcircuit has a repeater mode, in which the 12C bus signals from central processor are sent to an additional bus operating at frequencies up to 400 kHz. Using an additional bus, it is possible to control another microcircuit in slave mode. In our module this is an RF converter.

The STV0299B chip was designed in 2000. It was produced in a 64-pin TQFP package. To power it, two voltages are used: 3.3 V - for the input and output interfaces, and 2.5 V - for the analog part of the input ADC and the core.

The BS2F7VZ0194A module provides reception of DVB-S system signals with an input level in the range of -65...-25 dBm and a symbol rate from 2 to 45 Mbit/s and converts them into a TS transport stream. The convolutional Witterbi decoder of the internal code processes errors with values ​​1/2, 2/3, 3/4, 5/6, 7/8 with a code constraint length K = 7. Packet errors are monitored and corrected in the external Reed code decoder -Solomon. The module can operate at a temperature of 0...60 °C (storage temperature 20...+85°C) and humidity no more than 85% (during storage no more than 95%).

Designation of module pins and their functional purpose are indicated in table. 2. Module weight - 35 g.

For operation of the modules, voltages of 3.3 ± 0.165 and 2.5 ± 0.125 V are required. The current consumed from the sources does not exceed 200 and 350 mA, respectively. To ensure stability of the input circuits, the 3.3 V line is connected through a noise suppression filter to a separate voltage stabilizer.

The schematic diagram of the BS2F7VZ0194A NIM module (RF converter and QPSK demodulator) is shown in Fig. 8. The input IF signal from the external converter passes through the connector to the amplifier, which compensates for the signal attenuation in the reduction connecting cable. It is assembled on a microwave transistor VT1. The amplified signal from the amplifier output is supplied through a symmetrical divider-transformer on elements L8, L9, R8 to the output connector (bypass loop for connecting a second receiver) and to the RF converter D1. The low-pass filter on elements L1 L4, C4C6, C8 C13 prevents the penetration of microwave oscillations into the module’s power circuit.

The local oscillator signal of the required frequency is generated in the D1 chip using a PLL loop. It determines the frequency of the received channel, and its setting is provided via the 12C bus. The first AGC loop consists of a detector and conditioning amplifier in the QPSK demodulator D2, as well as a voltage-controlled executive amplifier in the D1 chip. The AGC system maintains the I and Q signals at the output of the RF converter at a constant level while the input signal varies over a wide range.

Chip D1 is controlled via the 12C bus through a repeater located in the demodulator D2. The operation of the components of the D1 microcircuit is synchronized by an exemplary oscillator stabilized by the BQ1 quartz resonator. The same oscillations are synchronized by the GPSK demodulator in D2.

The I and Q signals from the output of the RF converter D1 are supplied to the D2 chip, which converts them into transport signal TS. The input signal is digitized by an internal dual ADC, and the carrier and clock pulses are restored. The divider R24-R26 sets the voltage interval in which the input signals are converted. After ADC digital signal passes through the circuits to compensate for the offset of the DC component introduced into the input signals by the RF converter. At the output of the compensator, a detector of the first AGC loop is installed, which controls the adjustable input amplifier of the RF converter D1.

The digitized signals are sequentially passed through a Nyquist filter, an interpolator, a second internal digital AGC loop, as well as a Witterby decoder, Forney deinterleaving circuits, and a Reed-Solomon decoder. After error correction, the signal is processed in the energy dispersion compensator and in the synchroinverter. The received transport signal TS from the output of the microcircuit is sent to the output of the NIM module.

The corresponding nodes of the D2 chip evaluate the quality of the received channel, which is recorded in its registers. Its nodes are controlled via the GC bus. Using a bus repeater in D2 reduces the number of control lines for controlling D1 and D2 from four to two.

The core of the GPSK demodulator D2 module is powered by a voltage of +2.5 V, and the peripheral devices are powered by a voltage of +3.3 V. Supply voltages are supplied to the microcircuit according to the rule in which a voltage of +2.5 V is supplied first, and then +3 ,3 V. Turning off the supply voltage should be in the reverse order.
Control of the IX2476VA (D1) chip is provided by a standard 12C control interface. It operates at operating frequencies up to 400 kHz in fast mode. The microcircuit has four control addresses. They are selected by hardware, supplying the necessary constant pressure to the ADR output (ADRess select) according to table. 3. This function is designed to control multiple modules in multi-program applications. In the module being described, the write address of the microcircuit is COh, and the read address is C1h.

The local oscillator frequency, PLL loop parameters and other microcircuit settings are provided by sending five bytes of data via the 12C bus in accordance with Table. 4 when the RTS bit is set to 0 in the format

L2Sstart -> BYTE1 -> BYTE2 -> BYTES -> BYTE4 - BYTE5, where BYTE1 is the address of the IX25765VA chip. When a microcircuit is read, addresses with a read flag are sent to it. In response, the microcircuit outputs a byte containing the values ​​of the status register onto the 12C bus. It is read-only. Control registers are available for both writing and reading.

The required frequency of the local oscillator, which is a voltage-controlled oscillator (VCO) and covered by a PLL loop, is ensured in this way. The local oscillator oscillations are divided by a microwave prescaler with a division factor P (16 or 32). After the prescaler, an absorbing counter is switched on with settable coefficients of fixed N and variable A divisions in the intervals 5-255 and 0-31 (at A< N). Частота полученного сигнала сравнивается с частотой колебаний образцового генератора Fosc, делённой на коэффициент R. Напряжение ошибки воздействует на управляющий вход ГУН, стабилизируя его частоту.

The VCO frequency is calculated using the formula

FrYH = [(P*N) + A]*Fosc/R.

The division factor P of the prescaler is switched with the PSC bit. When the bit is set to 0, the coefficient is 32; when the bit is set to 1, it is 16. The absorption counter division coefficients N and A are set with bits N8-N1 and A5-A1, respectively. N values ​​less than five are prohibited. The frequency division factor R of the reference oscillator is switched with the REF bit. In case of significance
For bit 0, the coefficient is equal to 4, the value of bit 1 corresponds to coefficient 8. With a quartz resonator generation frequency of 4 MHz, the comparison frequency will be equal to 1 MHz and 500 kHz, respectively.

Bits DIV, BA2, BA1, B AO serve as calibration bits for the VCO (set the range of output signal generation frequencies): 1110 - 950... 1065 MHz; 1111 - 1065...1170 MHz; 0001 - 1170...1300 MHz; 0010- 1300...1445 MHz; 0011 - 1445.. 1607 MHz; 0100 - 1607...1778 MHz; 0101 - 1778...1942 MHz 0110 -1942... 2150 MHz.

Bits C1, CO determine the pump current of the control circuit in the PLL loop (default value - ±1200 µA): at 00 - ±120 µA, 01 -±260 µA, 10 - ±555 µA, 11 -±1200 µA.
The amplifier is set by bits BG1 and BG0. With a value of 00 or 01, the coefficient is 0 dB, at 10 2 dB, at

11 4 dB. Bits PD5, PD4, PD3, PD2

The bandwidth of the output low-pass filter components 6 and I of the QPSK output signal is determined. The low-pass filter bandwidth at the -3 dB level takes values ​​from 10 to 30 MHz in 2 MHz steps when changing bit values ​​from 0011 to 1101.

When the RTS bit is set to 0, the chip operates in normal mode, and if the value is 1, it goes into test mode.

The control bits of the status register are readable. A POR bit of 0 indicates that the chip is supplied with normal supply voltage (more than 2.2 V), and all registers are set to default. A value of 1 for this bit indicates that the supply voltage is below normal and the microcircuit is not functioning.

The FL bit of the control register determines whether the PLL loop has locked the desired frequency. If it is level 0, the PLL loop is in the capture state. When this bit is set to 1, the system is in error mode.

The STV0299B chip has a control address for writing D0h, and for reading - D1h.

As stated above, the DRS-4500 receivers use the EDS-1547FF1B+ module, which is described in detail in.

In the DRE-4500 receiver (see Fig. 3), the converter supply voltage (and, consequently, the reception polarization voltage) is formed by the DD5 LNBP13A microcircuit from ST Microelectronics, developed back in September 1998 and intended to work as in the then-removable operation of analogue receivers, as well as in newly introduced digital ones. In addition to this function, the microcircuit provides injection of a 22 kHz signal into the cable to switch reception subbands, as well as transmission of DiSEqC protocol signals generated by the QPSK demodulator of the NIM module.

The DD5 chip is controlled by the processor as part of DD1 along three lines: permission to supply voltage to the converter EN, selection of polarization VSEL (0 - converter supply voltage 13 V, 1 - 18 V), resolution of signal passage 22 kHz ENT (at 1). If the external converter exceeds the current consumption or short circuit in the reduction cable, transistor VT24 closes, and the processor determines the fault condition in the cable.

The receiver is designed in such a way that when it is switched to standby mode, control of the polarization of the converter and switching of reception subbands can be provided from the second slave receiver. However, when the main receiver is completely turned off, the power from the converter is also removed and the functioning of the slave receiver is disrupted, which, of course, seems to be a disadvantage of such a connection.

In the DRS-4500 receiver, the converter supply voltage and, consequently, the reception polarization is formed by a unit assembled on transistors VT17, \Ya28-VT30, VT35 and an adjustable linear voltage regulator DA1 microcircuit of the main board (see Fig. 4.1).

Control of the converter power supply and control over it is provided by the processor in the single-chip decoder DD1 along two lines: permission to supply voltage to LNB converter ENABLE (via switches on transistors VT30, VT35) and selection LNB polarization POL (switch on transistor VT17).

If the converter exceeds the current consumption or there is a short circuit in the reduction cable, the voltage on the divider R160R164 decreases, the processor reads the fault state in the connection.

When the receiver is switched to standby mode, control of the polarization of the converter and switching of subbands, as in the DRE-4500, can occur from the slave receiver. Transistors VT28, VT29 provide supply voltage from the slave receiver (13 or 18 V) to the converter. In the operating mode of the main receiver, the passage of voltage from the slave is blocked. When the main receiver is completely disconnected from the network, power is removed from the converter, and the functioning of the slave receiver is disrupted.

Through the R168C132 chain, a 22 kHz signal is injected into the downlink cable (to switch reception subbands) and DiSEqC protocol signals generated by the QPSK demodulator in the NIM module.

The RF converter and QPSK demodulator of the DM1 module in receivers are controlled via a separate 12C bus from the DD1 processor.

The digital parts of the DRE-4500 and DRS-4500 receivers are similar. The TS signal in the MPEG-4 or MPEG-2 standard from the output of the DM1 module (see Fig. 3 and 4.1) through the limiting resistor assemblies R39, R43 and R46 is supplied to the core module installed in the XS4 connector (SO DIMM 144). The core module works on the principle of CAM modules in client-server mode. At the same time, it uses the resources of the main processor DD1. Core modules will be discussed further below.

Elements of microcircuits DD3, DD4, DD6, DD7 provide the core module access interface to decoder resources
DD1. The switch is controlled by the processor in DD1. The descrambled TS stream is transmitted from the output of the core module to the input of the TS router in DD1 when receiving encoded programs or directly by the router of the NP4 (or NP4+) chip in the core module from the output of the NIM module to the TS router DD1 when receiving FTA channels or channels , encoded in the MPEG-2 standard.

The receiver is controlled by a 32-bit ST20 microcontroller, which serves as the core of the DD1 processor. Its EMI interface uses a 16 Mbit parallel DS2 FLASH-na-memory, into which the control program is written. The memory is a M29W160ET microcircuit from ST Microelectronics.

Change control program receivers is possible via the RS-232 interface. In this case, modification of the bootloader (BOOT sectors) does not occur. The pairing of the RS-232 interface levels and the input and output ports of the DD1 processor is provided by cascades on elements VT28-VT30, VD13, VD15 (see Fig. 3) and VT24, VT34, VD20 (see Fig. 4.1).

If it is necessary to completely rewrite (modify) the contents of DS2 (including BOOT sectors), use the method of programming FLASH memory via the JTAG interface. It is a 20-pin XP1 pin connector (the manufacturer did not install it on the board).

Connected to the 16-bit SMI interface in the DD1 processor dynamic RAM DS3 with a memory capacity of 64 Mbit (K4S641632K-UC60 chip from Samsung). It is used by the MPEG-2 decoder, control processor and digital encoder (DENC) in DD1.

The 27 MHz sample oscillation is generated by a voltage controlled master oscillator (VCO). It is assembled on a DD2 chip. The frequency is stabilized by the ZQ1 quartz resonator. From the reference frequency, the internal nodes of the DD1 processor generate frequencies for the operation of the core, other internal nodes, and external FLASH and SDRAM memory. When turned on, setting the receiver to its initial state (reset) is provided by a node on transistors VT1, VT2. Hard reset during repairs, this can be done by briefly short-circuiting the terminals of capacitor C57 to each other.

The DS1 EEPROM chip (24C64 from ATMEL) stores the current user settings. Its connection with the main controller occurs via the main 12C bus.

Digital signals soundtrack television programs are sent to the DA5 audio DAC, where they are converted into analog signals. Analog video and sound signals come to active buffer amplifiers.

Analog full color television signal processed by an amplifier using transistors VT6, VT8 and passes to the SCART connector and RF modulator DM3 (RF-H2170MUP from Wittis in DRE-4000 and TNF-0170U623R from Tenas in DRS-4500). Component signals R through an amplifier on transistors VT9, VT11, G on VT16, VT20 and B on VT15, VT19, together with a stereo audio signal that has passed the second-order low-pass filter DA4 and buffer amplifiers on transistors VT13, VT14, are also supplied to the SCART connector. The summed signal of stereo channels is fed through a buffer amplifier on transistor VT18 to an RF modulator, which transfers image and audio signals to any UHF channel. The modulator is controlled via the main 12C bus. Buffer amplifiers on transistors VT5 and VT7, VT10 and VT12 match the output
The Y and C component signals of the DD1 chip and the S-VIDEO XS2 connector.

As mentioned above, a core module is used to descramble transmissions encrypted in the DRE-CRYPT system and transcode audio and video signals encoded in the MPEG-4 standard into signals using the MPEG-2 system. Conditional access is provided by using a smart card, which is installed in a card reader connected to the HRZ connector of the main board. The node diagram is shown in Fig. 9.

The card accepts encoded core modules from the NP4 or NP4+ chip
CW (Cipher Word) CSA keys and issues decrypted DW (Decipher Word) keys. Coordination of the interface levels of the ISO-7816 smart card and the NP4 or NP4+ chip is ensured in a specialized core module chip.

The DRE-4500 receivers use core modules using the NP4 AVC decoder, and the DRS-4500 receivers use NP4+ chips. The software of both receivers can work with any core module based on these chips.

(To be continued)

How to set up the DRE-4500, DRS-4500, GS 7300 and DRE-5500 receiver. "Tricolor TV-Siberia" after April 22, 2014.

If Tricolor TV Siberia does not work for you or says there is no signal, then you need to update and configure your DRE-4500, DRS-4500 or DRE-5500 receiver.

This setting must be done in connection with the start of broadcasting of the Tricolor Siberia project from the new Express-AT1 satellite, which replaced Bonum and Direct.

First we need to write down old version firmware of your receiver.

To do this, in the main menu, go to the bottom icon called status.

After the firmware, the software version should become 2,2,215.

This firmware will be downloaded directly from the satellite.

Let's begin the process of updating the software of your Tricolor TA Siberia receiver.

1. Disconnect the receiver from the power outlet and plug it back in.

2. We need to turn on the TricolorTV news channel. This channel should be in the top ten channels.

After switching to Info. The channel should display a splash screen offering a software update from the satellite.

3.After pressing the OK button, the software update process will begin.

At the top there will be an inscription Updated from satellite. The update process should take approximately 5 minutes and during this time the receiver should not be disconnected from the network.

If you do this, you will have to take the receiver to a service center for repair or manual firmware.

4. When the software update process is completed, press the OK key on the remote control and after that the receiver will reboot.

5. After turning on the receiver, you will need to do the initial setup of the receiver and search for Tricolor Siberia channels.

6. Upon completion initial setup again go to the status menu and look there new version Your receiver's firmware is 2,2,215.

7. If the version is different from 2,2,215, then you need to return to point 1 of this article and do the update process again.

Here is a video instruction on how to set up the Tricolor Siberia receiver.

Dear subscribers!

By technical reasons There may be interruptions in signal reception for subscribers after maintenance work on January 21, 2015 from 02:00 to 10:00, which manifest themselves in the coding of Tricolor TV TV/radio channels.

If problems occur, you must reboot the receiving equipment.

If necessary, send reactivation commands.

We apologize for any inconvenience.

Your "Tricolor TV"

And if you have receiver models DRS–4500, DRE–4500, DRE–5500, then click HERE.

If you have other Tricolor models, click HERE.

1. Owners of receiving equipment models DRS–4500, DRE–4500, DRE–5500, CI7101s, as well as modules CAM-Siberia-DRE perform a reset to factory settings.

To do this, press “Menu” on the receiver’s remote control, select “Settings”, press the “OK” button, then “Manual search”, confirm the selection by pressing the “OK” button and specify in the window that appears following parameters:
Satellite name: Doesn't matter
Frequency: 12355
Polarization: Left
Flow rate: 21500
FEC: 1/2
Important! In point " Network search"should be set to "YES" ("Menu" - "Settings" - "Manual search" - "Advanced" - "Network search" - "YES").
Then you need to select “Start Search” in the “Manual Search” menu and click the “OK” button. Attention! For equipment not manufactured General Satellite, the settings path may vary. If, after re-searching for channels, the program list is not displayed correctly, then you need to clear the program list through “Menu” - “Settings” - “Channel Organization” and repeat the re-search again. We apologize for the inconvenience caused.

2. Owners of receiving equipment models GS–8300, GS–8300N, DRS-8300, GS–8300M, GS 8302, GS 8304, GS 8305, GS 8306, HD-9300, HD 9303, GS-8307,GS-8308, DRS -8308 reset to factory settings. Re-search for TV channels "Tricolor TV".
To do this, press “Menu” on the receiver’s remote control, select “Search for Tricolor TV channels” “OK” and update the list of TV channels, following the prompts on the TV screen.

On the night of February 3-4, 2014, from 2:00 to 10:00 (Moscow time), maintenance work will take place, during which the composition of the “Maximum HD” and “Optimum” packages in the DirecTV-1R satellite broadcast area will change. In order to increase the stability of the signal from the DirecTV-1R satellite, on the eve of the Winter Games, on the night of February 3-4, 2014 from 02:00 to 10:00 (Moscow time), work will be carried out, after which the broadcasting of TV channels will be suspended:
“Mother and Child”, “Nano TV”, “Much TV”, “India TV”, “RTG TV”, “Tonus TV”, “Zoo TV”, “Comedy TV”, “365 days”, “NSTV”, "OTV Chelyabinsk". Broadcasting of these TV channels will be resumed after the launch of a new satellite, scheduled according to information from the Federal State Unitary Enterprise "Space Communications" on March 4, 2014, its arrival at the station and testing the performance of the on-board equipment. Upon completion of the preventive work, in order to resume viewing other TV channels “Tricolor TV-Siberia” from 10:00 (Moscow time) 02/04/2013 you must:

Setup and repair of the Tricolor TV receiver in Bratsk, Padun, Energetika: Gidrostroiteley 57 t 270353.